Interface layers for high-k/Ge gate stacks: Are they necessary?

P. C. McIntyre; D. Chi; C. O. Chui; H. Kim; K. I. Seo; K. C. Saraswat; R. Sreenivasan; T. Sugawara; F. S. Aguirre-Testado; R. M. Wallace

doi:10.1149/1.2355849

Interface layers for high-k/Ge gate stacks: Are they necessary?

P. C. McIntyre, D. Chi, C. O. Chui, H. Kim, K. I. Seo, K. C. Saraswat, R. Sreenivasan, T. Sugawara, F. S. Aguirre-Testado, R. M. Wallace

Department of Advanced Materials Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

15 Scopus citations

Abstract

We discuss the effects of interface layers between high-k gate insulators and the Ge substrate on the electrical characteristics of Ge MOS devices. Our work has focused on both germanium oxynitride (GeO_xN_y) and tantalum oxynitride (TaO_xN_y) interface layers. We find that ultrathin interface layers of TaO_xN_y, a high permittivity diffusion barrier, produce greatly improved charge trapping characteristics and promising capacitance scaling for high-k/Ge gate stacks. Effects of interface layers on interface state density and the frequency dispersion of the capacitance-voltage (CV) behavior under inversion are also described. copyright The Electrochemical Society.

Original language	English
Title of host publication	SiGe and Ge
Subtitle of host publication	Materials, Processing, and Devices
Publisher	Electrochemical Society Inc.
Pages	519-530
Number of pages	12
Edition	7
ISBN (Electronic)	1566775078
DOIs	https://doi.org/10.1149/1.2355849
State	Published - 2006
Event	SiGe and Ge: Materials, Processing, and Devices - 210th Electrochemical Society Meeting - Cancun, Mexico Duration: 29 Oct 2006 → 3 Nov 2006

Publication series

Name	ECS Transactions
Number	7
Volume	3
ISSN (Print)	1938-5862
ISSN (Electronic)	1938-6737

Conference

Conference	SiGe and Ge: Materials, Processing, and Devices - 210th Electrochemical Society Meeting
Country/Territory	Mexico
City	Cancun
Period	29/10/06 → 3/11/06

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McIntyre, P. C., Chi, D., Chui, C. O., Kim, H., Seo, K. I., Saraswat, K. C., Sreenivasan, R., Sugawara, T., Aguirre-Testado, F. S., & Wallace, R. M. (2006). Interface layers for high-k/Ge gate stacks: Are they necessary? In SiGe and Ge: Materials, Processing, and Devices (7 ed., pp. 519-530). (ECS Transactions; Vol. 3, No. 7). Electrochemical Society Inc.. https://doi.org/10.1149/1.2355849

@inproceedings{fe2631c1bf464ca6ba4db94b3bc18331,

title = "Interface layers for high-k/Ge gate stacks: Are they necessary?",

abstract = "We discuss the effects of interface layers between high-k gate insulators and the Ge substrate on the electrical characteristics of Ge MOS devices. Our work has focused on both germanium oxynitride (GeOxNy) and tantalum oxynitride (TaOxNy) interface layers. We find that ultrathin interface layers of TaOxNy, a high permittivity diffusion barrier, produce greatly improved charge trapping characteristics and promising capacitance scaling for high-k/Ge gate stacks. Effects of interface layers on interface state density and the frequency dispersion of the capacitance-voltage (CV) behavior under inversion are also described. copyright The Electrochemical Society.",

author = "McIntyre, \{P. C.\} and D. Chi and Chui, \{C. O.\} and H. Kim and Seo, \{K. I.\} and Saraswat, \{K. C.\} and R. Sreenivasan and T. Sugawara and Aguirre-Testado, \{F. S.\} and Wallace, \{R. M.\}",

year = "2006",

doi = "10.1149/1.2355849",

language = "English",

series = "ECS Transactions",

publisher = "Electrochemical Society Inc.",

number = "7",

pages = "519--530",

booktitle = "SiGe and Ge",

edition = "7",

note = "SiGe and Ge: Materials, Processing, and Devices - 210th Electrochemical Society Meeting ; Conference date: 29-10-2006 Through 03-11-2006",

}

McIntyre, PC, Chi, D, Chui, CO, Kim, H, Seo, KI, Saraswat, KC, Sreenivasan, R, Sugawara, T, Aguirre-Testado, FS & Wallace, RM 2006, Interface layers for high-k/Ge gate stacks: Are they necessary? in SiGe and Ge: Materials, Processing, and Devices. 7 edn, ECS Transactions, no. 7, vol. 3, Electrochemical Society Inc., pp. 519-530, SiGe and Ge: Materials, Processing, and Devices - 210th Electrochemical Society Meeting, Cancun, Mexico, 29/10/06. https://doi.org/10.1149/1.2355849

TY - GEN

T1 - Interface layers for high-k/Ge gate stacks

T2 - SiGe and Ge: Materials, Processing, and Devices - 210th Electrochemical Society Meeting

AU - McIntyre, P. C.

AU - Chi, D.

AU - Chui, C. O.

AU - Kim, H.

AU - Seo, K. I.

AU - Saraswat, K. C.

AU - Sreenivasan, R.

AU - Sugawara, T.

AU - Aguirre-Testado, F. S.

AU - Wallace, R. M.

PY - 2006

Y1 - 2006

N2 - We discuss the effects of interface layers between high-k gate insulators and the Ge substrate on the electrical characteristics of Ge MOS devices. Our work has focused on both germanium oxynitride (GeOxNy) and tantalum oxynitride (TaOxNy) interface layers. We find that ultrathin interface layers of TaOxNy, a high permittivity diffusion barrier, produce greatly improved charge trapping characteristics and promising capacitance scaling for high-k/Ge gate stacks. Effects of interface layers on interface state density and the frequency dispersion of the capacitance-voltage (CV) behavior under inversion are also described. copyright The Electrochemical Society.

AB - We discuss the effects of interface layers between high-k gate insulators and the Ge substrate on the electrical characteristics of Ge MOS devices. Our work has focused on both germanium oxynitride (GeOxNy) and tantalum oxynitride (TaOxNy) interface layers. We find that ultrathin interface layers of TaOxNy, a high permittivity diffusion barrier, produce greatly improved charge trapping characteristics and promising capacitance scaling for high-k/Ge gate stacks. Effects of interface layers on interface state density and the frequency dispersion of the capacitance-voltage (CV) behavior under inversion are also described. copyright The Electrochemical Society.

UR - https://www.scopus.com/pages/publications/33846943704

U2 - 10.1149/1.2355849

DO - 10.1149/1.2355849

M3 - Conference contribution

AN - SCOPUS:33846943704

T3 - ECS Transactions

SP - 519

EP - 530

BT - SiGe and Ge

PB - Electrochemical Society Inc.

Y2 - 29 October 2006 through 3 November 2006

ER -

Interface layers for high-k/Ge gate stacks: Are they necessary?

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