Interface barrier abruptness and work function requirements for scaling Schottky source-drain MOS transistors

Naveen Agrawal, Jingde Chen, Zhao Hui, Yee Chia Yeo, Sungjoo Lee, Daniel S.H. Chan, Ming Fu Li, Ganesh S. Samudra

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Schottky source-drain (S/D) MOS transistor coupled with metal gate is a promising alternative to the conventional poly-Si gate and doped S/D MOSFET technology [1-2]. This paper explores through simulations the effect of metal S/D WF and the gradual change of barrier profile at the metal-semiconductor interface and in the few nanometers space around it on the n/p channel device performance. We present the S/D workfunction (WF) requirements for ultra short channel device design for the first time. Through modeling and fabrication, we also present the underlying physical explanation behind the existence of dual slope in Id-Vg characteristics of metal S/D and Gate MOSFETs.

Original languageEnglish
Title of host publication2006 International Conference on Simulation of Semiconductor Process and Devices, SISPAD '06
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages139-142
Number of pages4
ISBN (Print)1424404045, 9781424404049
DOIs
StatePublished - 2006
Externally publishedYes
Event2006 International Conference on Simulation of Semiconductor Process and Devices, SISPAD '06 - Monterey, CA, United States
Duration: 6 Sep 20068 Sep 2006

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Conference

Conference2006 International Conference on Simulation of Semiconductor Process and Devices, SISPAD '06
Country/TerritoryUnited States
CityMonterey, CA
Period6/09/068/09/06

Keywords

  • Dual slope
  • Metal gate
  • Metal source/drain
  • Schottky source-drain
  • TBGD

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