Improving the performance of multistage interconnection networks under nonuniform traffic pattern on shorter cycles

Multistage interconnection networks (MINs) have been recently identified as an efficient interconnection network for a switching fabric of communication structures such as gigabit ethernet switch, terabit router, and ATM switch. Even though there have been a number of studies about modeling MINs in the literature, almost all of them are for trends MINs under uniform traffic which dose not reflect the realistic. In this paper, we propose an analytical model to evaluate the performance of ATM switches based on MINs with the small clock cycle (SCC) scheme under nonuniform traffic. Here MINs of 6 and 10 stages with built-in buffer modules holding single or multiple cells are considered for the evaluation. Comprehensive computer simulation results present that the proposed model is effective for predicting the performance of ATM switches under the realistic nonuniform traffic. It also shows that the detrimental effect on the hot spot traffic which is typical in the Internet turns out to be more significant as the switch size increases.