High-reliability gate driver circuit to prevent ripple voltage

In this paper, a high-reliability gate driver circuit is proposed to prevent multiple outputs. The proposed circuit ensures reliability of the pull-up thin-film transistor (TFT) by periodically discharging the Q node voltage to the low-level voltage (VGL) in the off stage. In addition, the output node is composed of two pull-down TFTs that are driven alternately to ensure stability against bias stress. Thus, because the reliabilities of the pull-up and pull-down TFTs can be guaranteed simultaneously, the stability of the entire circuit is improved. Based on the simulation results, the rising and falling times of the output pulse are stable within 1.77 and 1.28 μs, respectively, even when the threshold voltage of the entire TFT is shifted by +10.0 V. In addition, the ripple voltage of the proposed circuit is almost eliminated and is within 0.79% of the total swing voltage. Moreover, through current is prevented in the proposed circuit because the turn-on durations of the pull-up and pull-down units are completely nonoverlapping, which suggests that unnecessary power consumption can be eliminated. Therefore, based on 2,160 stages, the total power consumption of the proposed circuit is reduced by 34.7 mW from 276.3 to 241.6 mW.