Hardware Architecture Design for Template Matching

Dong Wan Roh; Jae Wook Jeon

doi:10.1109/ISOCC47750.2019.9078515

Hardware Architecture Design for Template Matching

Dong Wan Roh, Jae Wook Jeon

Sungkyunkwan University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents the hardware architecture for ORB (Oriented FAST and Rotated BRIEF) based template matching that can overcome delay problems due to the high computation inherent in existing template matching techniques. The proposed method converts the extracted Canny edge image and FAST corner image into a bit string. It then compares the bit string data to locate the template image in the input image. Template matching is a technology used in various fields, such as object tracking and motion tracking. Because template matching has a long computation time, a solution to this issue has been widely researched in many industrial fields. To solve this problem, we designed a hardware structure based on XILINX Virtex7 (XC7V2000TT1FG1925-1 FPGA using Verilog-HDL).

Original language	English
Title of host publication	Proceedings - 2019 International SoC Design Conference, ISOCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	287-288
Number of pages	2
ISBN (Electronic)	9781728124780
DOIs	https://doi.org/10.1109/ISOCC47750.2019.9078515
State	Published - Oct 2019
Externally published	Yes
Event	16th International System-on-Chip Design Conference, ISOCC 2019 - Jeju, Korea, Republic of Duration: 6 Oct 2019 → 9 Oct 2019

Publication series

Name	Proceedings - 2019 International SoC Design Conference, ISOCC 2019
Volume	2019-January

Conference

Conference	16th International System-on-Chip Design Conference, ISOCC 2019
Country/Territory	Korea, Republic of
City	Jeju
Period	6/10/19 → 9/10/19

Keywords

FAST
FPGA
Key Points
Template Matching

Access to Document

10.1109/ISOCC47750.2019.9078515

Cite this

Wan Roh, D., & Wook Jeon, J. (2019). Hardware Architecture Design for Template Matching. In Proceedings - 2019 International SoC Design Conference, ISOCC 2019 (pp. 287-288). Article 9078515 (Proceedings - 2019 International SoC Design Conference, ISOCC 2019; Vol. 2019-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC47750.2019.9078515

@inproceedings{d70c97a6fec04985948a8914b4ef1a55,

title = "Hardware Architecture Design for Template Matching",

abstract = "This paper presents the hardware architecture for ORB (Oriented FAST and Rotated BRIEF) based template matching that can overcome delay problems due to the high computation inherent in existing template matching techniques. The proposed method converts the extracted Canny edge image and FAST corner image into a bit string. It then compares the bit string data to locate the template image in the input image. Template matching is a technology used in various fields, such as object tracking and motion tracking. Because template matching has a long computation time, a solution to this issue has been widely researched in many industrial fields. To solve this problem, we designed a hardware structure based on XILINX Virtex7 (XC7V2000TT1FG1925-1 FPGA using Verilog-HDL).",

keywords = "FAST, FPGA, Key Points, Template Matching",

author = "\{Wan Roh\}, Dong and \{Wook Jeon\}, Jae",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 16th International System-on-Chip Design Conference, ISOCC 2019 ; Conference date: 06-10-2019 Through 09-10-2019",

year = "2019",

month = oct,

doi = "10.1109/ISOCC47750.2019.9078515",

language = "English",

series = "Proceedings - 2019 International SoC Design Conference, ISOCC 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "287--288",

booktitle = "Proceedings - 2019 International SoC Design Conference, ISOCC 2019",

}

Wan Roh, D & Wook Jeon, J 2019, Hardware Architecture Design for Template Matching. in Proceedings - 2019 International SoC Design Conference, ISOCC 2019., 9078515, Proceedings - 2019 International SoC Design Conference, ISOCC 2019, vol. 2019-January, Institute of Electrical and Electronics Engineers Inc., pp. 287-288, 16th International System-on-Chip Design Conference, ISOCC 2019, Jeju, Korea, Republic of, 6/10/19. https://doi.org/10.1109/ISOCC47750.2019.9078515

Hardware Architecture Design for Template Matching. / Wan Roh, Dong; Wook Jeon, Jae.
Proceedings - 2019 International SoC Design Conference, ISOCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 287-288 9078515 (Proceedings - 2019 International SoC Design Conference, ISOCC 2019; Vol. 2019-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Hardware Architecture Design for Template Matching

AU - Wan Roh, Dong

AU - Wook Jeon, Jae

PY - 2019/10

Y1 - 2019/10

N2 - This paper presents the hardware architecture for ORB (Oriented FAST and Rotated BRIEF) based template matching that can overcome delay problems due to the high computation inherent in existing template matching techniques. The proposed method converts the extracted Canny edge image and FAST corner image into a bit string. It then compares the bit string data to locate the template image in the input image. Template matching is a technology used in various fields, such as object tracking and motion tracking. Because template matching has a long computation time, a solution to this issue has been widely researched in many industrial fields. To solve this problem, we designed a hardware structure based on XILINX Virtex7 (XC7V2000TT1FG1925-1 FPGA using Verilog-HDL).

AB - This paper presents the hardware architecture for ORB (Oriented FAST and Rotated BRIEF) based template matching that can overcome delay problems due to the high computation inherent in existing template matching techniques. The proposed method converts the extracted Canny edge image and FAST corner image into a bit string. It then compares the bit string data to locate the template image in the input image. Template matching is a technology used in various fields, such as object tracking and motion tracking. Because template matching has a long computation time, a solution to this issue has been widely researched in many industrial fields. To solve this problem, we designed a hardware structure based on XILINX Virtex7 (XC7V2000TT1FG1925-1 FPGA using Verilog-HDL).

KW - FAST

KW - FPGA

KW - Key Points

KW - Template Matching

UR - https://www.scopus.com/pages/publications/85084653758

U2 - 10.1109/ISOCC47750.2019.9078515

DO - 10.1109/ISOCC47750.2019.9078515

M3 - Conference contribution

AN - SCOPUS:85084653758

T3 - Proceedings - 2019 International SoC Design Conference, ISOCC 2019

SP - 287

EP - 288

BT - Proceedings - 2019 International SoC Design Conference, ISOCC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 16th International System-on-Chip Design Conference, ISOCC 2019

Y2 - 6 October 2019 through 9 October 2019

ER -

Hardware Architecture Design for Template Matching

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