Germanium nanowire metal-oxide-semiconductor field-effect transistor fabricated by complementary-metal-oxide-semiconductor-compatible process

J. W. Peng; N. Singh; G. Q. Lo; M. Bosman; C. M. Ng; S. J. Lee

doi:10.1109/TED.2010.2088125

Germanium nanowire metal-oxide-semiconductor field-effect transistor fabricated by complementary-metal-oxide-semiconductor-compatible process

J. W. Peng
, N. Singh
, G. Q. Lo
, M. Bosman
, C. M. Ng
, S. J. Lee

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

This work presents a complementary metaloxidesemiconductor-compatible topdown fabrication of Ge nanowires along with their integration into pMOSFETs with "HfO₂/TaN" high-k/metal gate stacks. Lateral Ge wires down to 14 nm in diameter are achieved using a two-step dry etch process on a high-quality epitaxial Ge layer. To improve the interface quality between the Ge nanowire and the HfO₂, thermally grown GeO₂ and epitaxial-Si shells are used as interlayers. Devices with a GeO₂ shell demonstrated excellent I_ON/_I OFF} ratios (>10₆), whereas the epitaxial-Si shell was found to improve the field-effect mobility of the holes in Ge nanowires to 254 cm₂V _-1.s_-1.

Original language	English
Article number	5634088
Pages (from-to)	74-79
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	58
Issue number	1
DOIs	https://doi.org/10.1109/TED.2010.2088125
State	Published - Jan 2011
Externally published	Yes

Keywords

Core/shell (C/S)
germanium (Ge)
metaloxidesemiconductor field-effect transistor (MOSFET)
nanowire (NW)
topdown

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10.1109/TED.2010.2088125

Cite this

@article{408408b26b83489da111dda85c3da24f,

title = "Germanium nanowire metal-oxide-semiconductor field-effect transistor fabricated by complementary-metal-oxide-semiconductor-compatible process",

abstract = "This work presents a complementary metaloxidesemiconductor-compatible topdown fabrication of Ge nanowires along with their integration into pMOSFETs with {"}HfO2/TaN{"} high-k/metal gate stacks. Lateral Ge wires down to 14 nm in diameter are achieved using a two-step dry etch process on a high-quality epitaxial Ge layer. To improve the interface quality between the Ge nanowire and the HfO2, thermally grown GeO2 and epitaxial-Si shells are used as interlayers. Devices with a GeO2 shell demonstrated excellent ION/I OFF\} ratios (>106), whereas the epitaxial-Si shell was found to improve the field-effect mobility of the holes in Ge nanowires to 254 cm2V -1.s-1.",

keywords = "Core/shell (C/S), germanium (Ge), metaloxidesemiconductor field-effect transistor (MOSFET), nanowire (NW), topdown",

author = "Peng, \{J. W.\} and N. Singh and Lo, \{G. Q.\} and M. Bosman and Ng, \{C. M.\} and Lee, \{S. J.\}",

year = "2011",

month = jan,

doi = "10.1109/TED.2010.2088125",

language = "English",

volume = "58",

pages = "74--79",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - Germanium nanowire metal-oxide-semiconductor field-effect transistor fabricated by complementary-metal-oxide-semiconductor-compatible process

AU - Peng, J. W.

AU - Singh, N.

AU - Lo, G. Q.

AU - Bosman, M.

AU - Ng, C. M.

AU - Lee, S. J.

PY - 2011/1

Y1 - 2011/1

N2 - This work presents a complementary metaloxidesemiconductor-compatible topdown fabrication of Ge nanowires along with their integration into pMOSFETs with "HfO2/TaN" high-k/metal gate stacks. Lateral Ge wires down to 14 nm in diameter are achieved using a two-step dry etch process on a high-quality epitaxial Ge layer. To improve the interface quality between the Ge nanowire and the HfO2, thermally grown GeO2 and epitaxial-Si shells are used as interlayers. Devices with a GeO2 shell demonstrated excellent ION/I OFF} ratios (>106), whereas the epitaxial-Si shell was found to improve the field-effect mobility of the holes in Ge nanowires to 254 cm2V -1.s-1.

AB - This work presents a complementary metaloxidesemiconductor-compatible topdown fabrication of Ge nanowires along with their integration into pMOSFETs with "HfO2/TaN" high-k/metal gate stacks. Lateral Ge wires down to 14 nm in diameter are achieved using a two-step dry etch process on a high-quality epitaxial Ge layer. To improve the interface quality between the Ge nanowire and the HfO2, thermally grown GeO2 and epitaxial-Si shells are used as interlayers. Devices with a GeO2 shell demonstrated excellent ION/I OFF} ratios (>106), whereas the epitaxial-Si shell was found to improve the field-effect mobility of the holes in Ge nanowires to 254 cm2V -1.s-1.

KW - Core/shell (C/S)

KW - germanium (Ge)

KW - metaloxidesemiconductor field-effect transistor (MOSFET)

KW - nanowire (NW)

KW - topdown

UR - https://www.scopus.com/pages/publications/78650853238

U2 - 10.1109/TED.2010.2088125

DO - 10.1109/TED.2010.2088125

M3 - Article

AN - SCOPUS:78650853238

SN - 0018-9383

VL - 58

SP - 74

EP - 79

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 1

M1 - 5634088

ER -

Germanium nanowire metal-oxide-semiconductor field-effect transistor fabricated by complementary-metal-oxide-semiconductor-compatible process

Abstract

Keywords

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