Gate engineering to improve effective resistance of 28-nm high-k metal gate CMOS devices

In this paper, we report the development of a high-k/metal gate stacking process to reduce the effective gate resistance, and circuit level validation results in 28-nm gate first integrated high-k/metal gate CMOS devices. To achieve this, millisecond annealing was adopted and the silicon (Si) gate and TiN gate electrode thicknesses were controlled. The recrystallized poly-Si gate by millisecond annealing improved the performance of the ring oscillator (RO) by 15% and the minimum operating voltage (V_min) of the high-frequency test pattern (HFTP) by 34 mV. The poly-Si gate improved the uniformity of the boron concentration and suppressed localized low doping area at the bottom of the gate. When the Si gate thickness was reduced by 10 Å with respect to the reference (POR) value, the performance of the RO improved by 5% and V_min of HFTP improved by 20 mV due to the shorter boron diffusion distance. A 10-Å thicker TiN gate electrode improved V_min of HFTP by 30 mV, since the thicker TiN reduced the TiN/Si gate interface resistance.