TY - GEN
T1 - Fully Randomized 4-Channel 30 Gb/s Differential PRBS Generator with Single Clock Input and Different Channel Seed Settings
T2 - 17th International System-on-Chip Design Conference, ISOCC 2020
AU - Abbas, Waseem
AU - Seo, Munkyo
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/21
Y1 - 2020/10/21
N2 - A 4-channel low power 27-1 differential Pseudo Random Bit Sequence Generator is designed in a 28 nm CMOS process. It works with different seed settings for each channel using a single clock input, which makes it suitable for testing advanced communication systems such as QPSK transmitters. A simulated data rate of up to 30 Gb/s is achieved for all 4-channel. The Current Mode Logic is used for D Flip-Flop formation. A single channel consumes 48 mW power with 1.2 V power supply. The active chip area is 0.05 mm2, while with probing pads, it is 1.2 mm2.
AB - A 4-channel low power 27-1 differential Pseudo Random Bit Sequence Generator is designed in a 28 nm CMOS process. It works with different seed settings for each channel using a single clock input, which makes it suitable for testing advanced communication systems such as QPSK transmitters. A simulated data rate of up to 30 Gb/s is achieved for all 4-channel. The Current Mode Logic is used for D Flip-Flop formation. A single channel consumes 48 mW power with 1.2 V power supply. The active chip area is 0.05 mm2, while with probing pads, it is 1.2 mm2.
KW - CMOS
KW - Current Mode Logic (CML)
KW - Low Power
KW - Pseudo Random Binary Sequence Generator (PRBSG)
UR - https://www.scopus.com/pages/publications/85100716671
U2 - 10.1109/ISOCC50952.2020.9333114
DO - 10.1109/ISOCC50952.2020.9333114
M3 - Conference contribution
AN - SCOPUS:85100716671
T3 - Proceedings - International SoC Design Conference, ISOCC 2020
SP - 280
EP - 281
BT - Proceedings - International SoC Design Conference, ISOCC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 21 October 2020 through 24 October 2020
ER -