First Demonstration of Innovative 3D AND-Type Fully-Parallel Convolution Block with Ultra-High Area-and Energy-Efficiency

Jangsaeng Kim; Jiseong Im; Jonghyun Ko; Soochang Lee; Dongseok Kwon; Wonjun Shin; Joon Hwang; Ryun Han Koo; Woo Young Choi; Jong Ho Lee

doi:10.1109/IEDM45741.2023.10413852

First Demonstration of Innovative 3D AND-Type Fully-Parallel Convolution Block with Ultra-High Area-and Energy-Efficiency

Jangsaeng Kim
, Jiseong Im
, Jonghyun Ko
, Soochang Lee
, Dongseok Kwon
, Wonjun Shin
, Joon Hwang
, Ryun Han Koo
, Woo Young Choi
, Jong Ho Lee

Seoul National University
Samsung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

We propose for the first time a novel 3D AND-type flash memory array for a fully-parallel convolution block (FPCB) designed to realize compute-in-memory technology. By leveraging the structural advantages of 3D AND-type cells, the FPCB achieves area- and energy-efficient convolution and fully-connected operations with full memory utilization. In the convolution operation, the FPCB significantly reduces the number of cells and line resistance by a factor of about 10^-4 or less (for the ImageNet dataset). Compared to conventional crossbars, the FPCB reduces ~96% and ~74% of area occupancy and energy consumption, respectively.

Original language	English
Title of host publication	2023 International Electron Devices Meeting, IEDM 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350327670
DOIs	https://doi.org/10.1109/IEDM45741.2023.10413852
State	Published - 2023
Externally published	Yes
Event	2023 International Electron Devices Meeting, IEDM 2023 - San Francisco, United States Duration: 9 Dec 2023 → 13 Dec 2023

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	2023 International Electron Devices Meeting, IEDM 2023
Country/Territory	United States
City	San Francisco
Period	9/12/23 → 13/12/23

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Access to Document

10.1109/IEDM45741.2023.10413852

Cite this

Kim, J., Im, J., Ko, J., Lee, S., Kwon, D., Shin, W., Hwang, J., Koo, R. H., Choi, W. Y., & Lee, J. H. (2023). First Demonstration of Innovative 3D AND-Type Fully-Parallel Convolution Block with Ultra-High Area-and Energy-Efficiency. In 2023 International Electron Devices Meeting, IEDM 2023 (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM45741.2023.10413852

@inproceedings{8269ac8987a046f7b39c2bf532d0c647,

title = "First Demonstration of Innovative 3D AND-Type Fully-Parallel Convolution Block with Ultra-High Area-and Energy-Efficiency",

abstract = "We propose for the first time a novel 3D AND-type flash memory array for a fully-parallel convolution block (FPCB) designed to realize compute-in-memory technology. By leveraging the structural advantages of 3D AND-type cells, the FPCB achieves area- and energy-efficient convolution and fully-connected operations with full memory utilization. In the convolution operation, the FPCB significantly reduces the number of cells and line resistance by a factor of about 10-4 or less (for the ImageNet dataset). Compared to conventional crossbars, the FPCB reduces \textasciitilde{}96\% and \textasciitilde{}74\% of area occupancy and energy consumption, respectively.",

author = "Jangsaeng Kim and Jiseong Im and Jonghyun Ko and Soochang Lee and Dongseok Kwon and Wonjun Shin and Joon Hwang and Koo, \{Ryun Han\} and Choi, \{Woo Young\} and Lee, \{Jong Ho\}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 International Electron Devices Meeting, IEDM 2023 ; Conference date: 09-12-2023 Through 13-12-2023",

year = "2023",

doi = "10.1109/IEDM45741.2023.10413852",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 International Electron Devices Meeting, IEDM 2023",

}

Kim, J, Im, J, Ko, J, Lee, S, Kwon, D, Shin, W, Hwang, J, Koo, RH, Choi, WY & Lee, JH 2023, First Demonstration of Innovative 3D AND-Type Fully-Parallel Convolution Block with Ultra-High Area-and Energy-Efficiency. in 2023 International Electron Devices Meeting, IEDM 2023. Technical Digest - International Electron Devices Meeting, IEDM, Institute of Electrical and Electronics Engineers Inc., 2023 International Electron Devices Meeting, IEDM 2023, San Francisco, United States, 9/12/23. https://doi.org/10.1109/IEDM45741.2023.10413852

First Demonstration of Innovative 3D AND-Type Fully-Parallel Convolution Block with Ultra-High Area-and Energy-Efficiency. / Kim, Jangsaeng; Im, Jiseong; Ko, Jonghyun et al.
2023 International Electron Devices Meeting, IEDM 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - First Demonstration of Innovative 3D AND-Type Fully-Parallel Convolution Block with Ultra-High Area-and Energy-Efficiency

AU - Kim, Jangsaeng

AU - Im, Jiseong

AU - Ko, Jonghyun

AU - Lee, Soochang

AU - Kwon, Dongseok

AU - Shin, Wonjun

AU - Hwang, Joon

AU - Koo, Ryun Han

AU - Choi, Woo Young

AU - Lee, Jong Ho

PY - 2023

Y1 - 2023

N2 - We propose for the first time a novel 3D AND-type flash memory array for a fully-parallel convolution block (FPCB) designed to realize compute-in-memory technology. By leveraging the structural advantages of 3D AND-type cells, the FPCB achieves area- and energy-efficient convolution and fully-connected operations with full memory utilization. In the convolution operation, the FPCB significantly reduces the number of cells and line resistance by a factor of about 10-4 or less (for the ImageNet dataset). Compared to conventional crossbars, the FPCB reduces ~96% and ~74% of area occupancy and energy consumption, respectively.

AB - We propose for the first time a novel 3D AND-type flash memory array for a fully-parallel convolution block (FPCB) designed to realize compute-in-memory technology. By leveraging the structural advantages of 3D AND-type cells, the FPCB achieves area- and energy-efficient convolution and fully-connected operations with full memory utilization. In the convolution operation, the FPCB significantly reduces the number of cells and line resistance by a factor of about 10-4 or less (for the ImageNet dataset). Compared to conventional crossbars, the FPCB reduces ~96% and ~74% of area occupancy and energy consumption, respectively.

UR - https://www.scopus.com/pages/publications/85185599702

U2 - 10.1109/IEDM45741.2023.10413852

DO - 10.1109/IEDM45741.2023.10413852

M3 - Conference contribution

AN - SCOPUS:85185599702

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2023 International Electron Devices Meeting, IEDM 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2023 International Electron Devices Meeting, IEDM 2023

Y2 - 9 December 2023 through 13 December 2023

ER -

Kim J, Im J, Ko J, Lee S, Kwon D, Shin W et al. First Demonstration of Innovative 3D AND-Type Fully-Parallel Convolution Block with Ultra-High Area-and Energy-Efficiency. In 2023 International Electron Devices Meeting, IEDM 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM45741.2023.10413852

First Demonstration of Innovative 3D AND-Type Fully-Parallel Convolution Block with Ultra-High Area-and Energy-Efficiency

Abstract

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