Fabrication of high Ge content SiGe layer on Si by Ge condensation technique

S. Balakumar; T. Jun Wei; C. H. Tung; G. Q. Lo; H. S. Nguyen; C. S. Fong; A. Agarwal; R. Kumar; N. Balasubramanian; S. J. Lee; D. L. Kwong

doi:10.1109/IPFA.2006.251050

Fabrication of high Ge content SiGe layer on Si by Ge condensation technique

S. Balakumar
, T. Jun Wei
, C. H. Tung
, G. Q. Lo
, H. S. Nguyen
, C. S. Fong
, A. Agarwal
, R. Kumar
, N. Balasubramanian
, S. J. Lee
, D. L. Kwong

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Original language	English
Title of host publication	Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006
Pages	301-305
Number of pages	5
DOIs	https://doi.org/10.1109/IPFA.2006.251050
State	Published - 2006
Externally published	Yes
Event	13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006 - Singapore, Singapore Duration: 3 Jul 2006 → 7 Jul 2006

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference	13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006
Country/Territory	Singapore
City	Singapore
Period	3/07/06 → 7/07/06

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10.1109/IPFA.2006.251050

Cite this

Balakumar, S., Jun Wei, T., Tung, C. H., Lo, G. Q., Nguyen, H. S., Fong, C. S., Agarwal, A., Kumar, R., Balasubramanian, N., Lee, S. J., & Kwong, D. L. (2006). Fabrication of high Ge content SiGe layer on Si by Ge condensation technique. In Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006 (pp. 301-305). Article 4017075 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2006.251050

Balakumar, S. ; Jun Wei, T. ; Tung, C. H. et al. / Fabrication of high Ge content SiGe layer on Si by Ge condensation technique. Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006. 2006. pp. 301-305 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{73a9caaf949940afb217c29386e8d5be,

title = "Fabrication of high Ge content SiGe layer on Si by Ge condensation technique",

author = "S. Balakumar and \{Jun Wei\}, T. and Tung, \{C. H.\} and Lo, \{G. Q.\} and Nguyen, \{H. S.\} and Fong, \{C. S.\} and A. Agarwal and R. Kumar and N. Balasubramanian and Lee, \{S. J.\} and Kwong, \{D. L.\}",

year = "2006",

doi = "10.1109/IPFA.2006.251050",

language = "English",

isbn = "1424402069",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

pages = "301--305",

booktitle = "Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006",

note = "13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006 ; Conference date: 03-07-2006 Through 07-07-2006",

}

Balakumar, S, Jun Wei, T, Tung, CH, Lo, GQ, Nguyen, HS, Fong, CS, Agarwal, A, Kumar, R, Balasubramanian, N, Lee, SJ & Kwong, DL 2006, Fabrication of high Ge content SiGe layer on Si by Ge condensation technique. in Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006., 4017075, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, pp. 301-305, 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006, Singapore, Singapore, 3/07/06. https://doi.org/10.1109/IPFA.2006.251050

Fabrication of high Ge content SiGe layer on Si by Ge condensation technique. / Balakumar, S.; Jun Wei, T.; Tung, C. H. et al.
Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006. 2006. p. 301-305 4017075 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Fabrication of high Ge content SiGe layer on Si by Ge condensation technique

AU - Balakumar, S.

AU - Jun Wei, T.

AU - Tung, C. H.

AU - Lo, G. Q.

AU - Nguyen, H. S.

AU - Fong, C. S.

AU - Agarwal, A.

AU - Kumar, R.

AU - Balasubramanian, N.

AU - Lee, S. J.

AU - Kwong, D. L.

PY - 2006

Y1 - 2006

UR - https://www.scopus.com/pages/publications/34250637204

U2 - 10.1109/IPFA.2006.251050

DO - 10.1109/IPFA.2006.251050

M3 - Conference contribution

AN - SCOPUS:34250637204

SN - 1424402069

SN - 9781424402069

T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

SP - 301

EP - 305

BT - Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006

T2 - 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006

Y2 - 3 July 2006 through 7 July 2006

ER -

Balakumar S, Jun Wei T, Tung CH, Lo GQ, Nguyen HS, Fong CS et al. Fabrication of high Ge content SiGe layer on Si by Ge condensation technique. In Proceedings of 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2006. 2006. p. 301-305. 4017075. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2006.251050

Fabrication of high Ge content SiGe layer on Si by Ge condensation technique

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