Fabrication and defect-driven analysis of CMOS inverters using SnO_x/ZnO TFTs: Implications for balanced performance

The advance of System-on-Panel technology has enabled the integration of CMOS inverters to drive high-performance OLED and micro LED displays. Conventional two n–type TFT configurations in display drivers suffer from a voltage drop (V_DD–V_Th), resulting in diminished output intensity. To address this limitation, integrating a CMOS inverter comprising both p–type and n–type TFTs offers a promising solution. However, these CMOS inverters face issues, such as asymmetric switching, reduced gain, and diminished noise margin, primarily attributed to the poor electrical performance of the p–type TFTs. While previous studies on CMOS inverters have mainly addressed p–type TFT performance enhancement using various fabrication strategies, the route to improve performance by tuning the material defect density of states has remained unexplored. This work shows the performance disparity between the fabricated p–type SnO TFT and n–type ZnO TFTs, and integrates these TFTs into a CMOS inverter. Electrical characterization reveals good symmetry in threshold voltage (V_Th) between SnO_x and ZnO TFTs, which is essential for CMOS operation. The fabricated CMOS inverter demonstrates a maximum voltage gain of ∼ −10.5 at V_DD = 10 V, with stable switching behavior. Using TCAD simulations based on fabricated device parameters, we identify two key factors affecting inverter performance: deep acceptor states in SnO causing V_Th shifts, and the decay energy of donor-like tail states influencing voltage gain. These findings provide critical insights into optimizing oxide-based CMOS inverters, while highlighting the challenges in achieving balanced p–type and n–type TFT performance.