TY - GEN
T1 - Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators
AU - Singh, Arvind
AU - Kar, Monodeep
AU - Ko, Jong Hwan
AU - Mukhopadhyay, Saibal
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/9/21
Y1 - 2015/9/21
N2 - The power attack protection of encryption engines often comes at the expense of area, power, and/or performance overheads making the design of a low-power and compact but secure encryption engine challenging. This paper explores the feasibility of using an on-chip low dropout regulator (LDO) as a countermeasure to power attack of low-power and compact encryption engine. We design an area minimized implementation of Advanced Encryption Standard (AES) using predictive 45nm node and show that lightweight implementations are more susceptible to power attack. Using behavioral modeling, we show that an on-chip LDO can enhance power attack resistance of this compact AES engine; however, the tradeoff between LDO performance and power attack protection is essential. Our analysis shows that LDO can increase power attack resistance of the compact AES by >800X with marginal area (1.4%) and power (5%) overheads.
AB - The power attack protection of encryption engines often comes at the expense of area, power, and/or performance overheads making the design of a low-power and compact but secure encryption engine challenging. This paper explores the feasibility of using an on-chip low dropout regulator (LDO) as a countermeasure to power attack of low-power and compact encryption engine. We design an area minimized implementation of Advanced Encryption Standard (AES) using predictive 45nm node and show that lightweight implementations are more susceptible to power attack. Using behavioral modeling, we show that an on-chip LDO can enhance power attack resistance of this compact AES engine; however, the tradeoff between LDO performance and power attack protection is essential. Our analysis shows that LDO can increase power attack resistance of the compact AES by >800X with marginal area (1.4%) and power (5%) overheads.
KW - Hardware Security
KW - IoT security
KW - Lightweight Cryptography
KW - Side Channel Attack
UR - https://www.scopus.com/pages/publications/84958549490
U2 - 10.1109/ISLPED.2015.7273503
DO - 10.1109/ISLPED.2015.7273503
M3 - Conference contribution
AN - SCOPUS:84958549490
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
SP - 134
EP - 139
BT - Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015
Y2 - 22 July 2015 through 24 July 2015
ER -