Etching of TiN-based gates for advanced complementary metal-oxide- semiconductor devices

V. Bliznetsov; N. Singh; R. Kumar; N. Balasubramanian; P. Guo; S. J. Lee; Y. Cai

doi:10.1116/1.2953732

Etching of TiN-based gates for advanced complementary metal-oxide- semiconductor devices

V. Bliznetsov
, N. Singh
, R. Kumar
, N. Balasubramanian
, P. Guo
, S. J. Lee
, Y. Cai

Agency for Science, Technology and Research, Singapore
National University of Singapore
Ngee Ann Polytechnic

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

This article presents results of study and optimization of plasma etching of TiN and TiN-TaN gates for sub-45 mm CMOS technology. By design of experiment in decoupled plasma source using HBr/Cl₂ plasma, etching parameters were established providing smooth post-etch surface.

Original language	English
Pages (from-to)	1440-1444
Number of pages	5
Journal	Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
Volume	26
Issue number	4
DOIs	https://doi.org/10.1116/1.2953732
State	Published - 2008
Externally published	Yes

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title = "Etching of TiN-based gates for advanced complementary metal-oxide- semiconductor devices",

abstract = "This article presents results of study and optimization of plasma etching of TiN and TiN-TaN gates for sub-45 mm CMOS technology. By design of experiment in decoupled plasma source using HBr/Cl2 plasma, etching parameters were established providing smooth post-etch surface.",

author = "V. Bliznetsov and N. Singh and R. Kumar and N. Balasubramanian and P. Guo and Lee, \{S. J.\} and Y. Cai",

year = "2008",

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language = "English",

volume = "26",

pages = "1440--1444",

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T1 - Etching of TiN-based gates for advanced complementary metal-oxide- semiconductor devices

AU - Bliznetsov, V.

AU - Singh, N.

AU - Kumar, R.

AU - Balasubramanian, N.

AU - Guo, P.

AU - Lee, S. J.

AU - Cai, Y.

PY - 2008

Y1 - 2008

N2 - This article presents results of study and optimization of plasma etching of TiN and TiN-TaN gates for sub-45 mm CMOS technology. By design of experiment in decoupled plasma source using HBr/Cl2 plasma, etching parameters were established providing smooth post-etch surface.

AB - This article presents results of study and optimization of plasma etching of TiN and TiN-TaN gates for sub-45 mm CMOS technology. By design of experiment in decoupled plasma source using HBr/Cl2 plasma, etching parameters were established providing smooth post-etch surface.

UR - https://www.scopus.com/pages/publications/49749141683

U2 - 10.1116/1.2953732

DO - 10.1116/1.2953732

M3 - Article

AN - SCOPUS:49749141683

SN - 1071-1023

VL - 26

SP - 1440

EP - 1444

JO - Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

JF - Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures

IS - 4

ER -

Etching of TiN-based gates for advanced complementary metal-oxide- semiconductor devices

Abstract

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