ESD Device Design Strategy for High Speed I/O in 45nm SOI Technology

Shuqing Cao; Akram A. Salman; Stephen G. Beebe; Mario M. Pelella; Jung Hoon Chun; Robert W. Dutton

ESD Device Design Strategy for High Speed I/O in 45nm SOI Technology

Shuqing Cao, Akram A. Salman, Stephen G. Beebe, Mario M. Pelella, Jung Hoon Chun, Robert W. Dutton

Department of Semiconductor Systems Engineering

Research output: Contribution to journal › Conference article › peer-review

6 Scopus citations

Abstract

This work focuses on characterization, modeling, and design of three different ESD protection devices for high-speed I/O applications in 45nm silicon-on-insulator (SOI) technology. In this paper, the gated diode, the bulk substrate diode, and a double-well field-effect diode are evaluated using very fast transmission line pulse (VF-TLP) test method.

Original language	English
Article number	4772139
Pages (from-to)	235-241
Number of pages	7
Journal	Electrical Overstress/Electrostatic Discharge Symposium Proceedings
State	Published - 2008
Event	2008 30th Annual on Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2008 - Tucson, AZ, United States Duration: 7 Sep 2008 → 12 Sep 2008

Cite this

@article{a56a58c93157480889ab412d7d013046,

title = "ESD Device Design Strategy for High Speed I/O in 45nm SOI Technology",

abstract = "This work focuses on characterization, modeling, and design of three different ESD protection devices for high-speed I/O applications in 45nm silicon-on-insulator (SOI) technology. In this paper, the gated diode, the bulk substrate diode, and a double-well field-effect diode are evaluated using very fast transmission line pulse (VF-TLP) test method.",

author = "Shuqing Cao and Salman, \{Akram A.\} and Beebe, \{Stephen G.\} and Pelella, \{Mario M.\} and Chun, \{Jung Hoon\} and Dutton, \{Robert W.\}",

year = "2008",

language = "English",

pages = "235--241",

journal = "Electrical Overstress/Electrostatic Discharge Symposium Proceedings",

issn = "0739-5159",

publisher = "ESD Association",

note = "2008 30th Annual on Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2008 ; Conference date: 07-09-2008 Through 12-09-2008",

}

TY - JOUR

T1 - ESD Device Design Strategy for High Speed I/O in 45nm SOI Technology

AU - Cao, Shuqing

AU - Salman, Akram A.

AU - Beebe, Stephen G.

AU - Pelella, Mario M.

AU - Chun, Jung Hoon

AU - Dutton, Robert W.

PY - 2008

Y1 - 2008

N2 - This work focuses on characterization, modeling, and design of three different ESD protection devices for high-speed I/O applications in 45nm silicon-on-insulator (SOI) technology. In this paper, the gated diode, the bulk substrate diode, and a double-well field-effect diode are evaluated using very fast transmission line pulse (VF-TLP) test method.

AB - This work focuses on characterization, modeling, and design of three different ESD protection devices for high-speed I/O applications in 45nm silicon-on-insulator (SOI) technology. In this paper, the gated diode, the bulk substrate diode, and a double-well field-effect diode are evaluated using very fast transmission line pulse (VF-TLP) test method.

UR - https://www.scopus.com/pages/publications/66649085199

M3 - Conference article

AN - SCOPUS:66649085199

SN - 0739-5159

SP - 235

EP - 241

JO - Electrical Overstress/Electrostatic Discharge Symposium Proceedings

JF - Electrical Overstress/Electrostatic Discharge Symposium Proceedings

M1 - 4772139

T2 - 2008 30th Annual on Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2008

Y2 - 7 September 2008 through 12 September 2008

ER -

ESD Device Design Strategy for High Speed I/O in 45nm SOI Technology

Abstract

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