Electrical properties of the HfO₂/Al₂O₃ dielectrics stacked using single- And dual-temperature atomic-layer deposition processes on In_0.53Ga_0.47As

For sequential stacking of an Al₂O₃ passivation layer and a main HfO₂ gate dielectric layer on In_0.53Ga_0.47As, we used single- and dual-temperature atomic-layer deposition processes, and systematically compared their effects on the dielectric-related electrical properties. When the deposition of Al₂O₃ passivation layer (approximately 0.7-0.8 nm) took place at relatively low temperatures of 100 °C, an increase in the subsequent deposition temperature for HfO₂ (from 100 to 300 °C) assisted in decreasing both capacitance-equivalent oxide thickness and the number of bulk-related traps. However, the valuable reduction in both near-interface defect density and leakage current through the low-temperature Al₂O₃ passivation approach was monotonically lessened with an increase in the process temperature for the subsequent HfO₂ deposition, which suggests the need for a careful optimization of a thermal budget for the dual-temperature process.