Dual-poly CVD HfO2 gate stack for sub-100 nm CMOS technology

S. J. Lee; C. H. Lee; Y. H. Kim; H. F. Luan; W. P. Bai; T. S. Jeon; D. L. Kwong

doi:10.1109/IWGI.2001.967552

Dual-poly CVD HfO₂ gate stack for sub-100 nm CMOS technology

S. J. Lee, C. H. Lee, Y. H. Kim, H. F. Luan, W. P. Bai, T. S. Jeon, D. L. Kwong

University of Texas at Austin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In this paper, the materials and processing challenges for the fabrication of high-quality, ultra-thin (EOT<1 nm) dual-poly high-k gate stack for sub-100 nm CMOS technology are reviewed along with recent results on CVD HfO₂. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve the thinnest possible EOT (equivalent oxide thickness) is discussed. Results are presented on the thermal stability of high-k materials, and interfacial reactions of high-k/Si and high-k/gate electrode interfaces. We also discuss key factors that govern the conduction and degradation mechanisms in high-k gate stacks. Finally, recent work on metal nitrides as possible gate electrode materials is reviewed and the upper thermal budget limit for such materials is discussed.

Original language	English
Title of host publication	Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	80-85
Number of pages	6
ISBN (Electronic)	4891140216, 9784891140212
DOIs	https://doi.org/10.1109/IWGI.2001.967552
State	Published - 2001
Externally published	Yes
Event	International Workshop on Gate Insulator, IWGI 2001 - Tokyo, Japan Duration: 1 Nov 2001 → 2 Nov 2001

Publication series

Name	Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001

Conference

Conference	International Workshop on Gate Insulator, IWGI 2001
Country/Territory	Japan
City	Tokyo
Period	1/11/01 → 2/11/01

Access to Document

10.1109/IWGI.2001.967552

Cite this

Lee, S. J., Lee, C. H., Kim, Y. H., Luan, H. F., Bai, W. P., Jeon, T. S., & Kwong, D. L. (2001). Dual-poly CVD HfO₂ gate stack for sub-100 nm CMOS technology. In Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001 (pp. 80-85). Article 967552 (Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IWGI.2001.967552

@inproceedings{7811abd79ae748fe9f2a13a3b9109165,

title = "Dual-poly CVD HfO2 gate stack for sub-100 nm CMOS technology",

abstract = "In this paper, the materials and processing challenges for the fabrication of high-quality, ultra-thin (EOT<1 nm) dual-poly high-k gate stack for sub-100 nm CMOS technology are reviewed along with recent results on CVD HfO2. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve the thinnest possible EOT (equivalent oxide thickness) is discussed. Results are presented on the thermal stability of high-k materials, and interfacial reactions of high-k/Si and high-k/gate electrode interfaces. We also discuss key factors that govern the conduction and degradation mechanisms in high-k gate stacks. Finally, recent work on metal nitrides as possible gate electrode materials is reviewed and the upper thermal budget limit for such materials is discussed.",

author = "Lee, \{S. J.\} and Lee, \{C. H.\} and Kim, \{Y. H.\} and Luan, \{H. F.\} and Bai, \{W. P.\} and Jeon, \{T. S.\} and Kwong, \{D. L.\}",

note = "Publisher Copyright: {\textcopyright} 2001 Japan Soc of Applied Physics.; International Workshop on Gate Insulator, IWGI 2001 ; Conference date: 01-11-2001 Through 02-11-2001",

year = "2001",

doi = "10.1109/IWGI.2001.967552",

language = "English",

series = "Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "80--85",

booktitle = "Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001",

}

Lee, SJ, Lee, CH, Kim, YH, Luan, HF, Bai, WP, Jeon, TS & Kwong, DL 2001, Dual-poly CVD HfO₂ gate stack for sub-100 nm CMOS technology. in Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001., 967552, Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001, Institute of Electrical and Electronics Engineers Inc., pp. 80-85, International Workshop on Gate Insulator, IWGI 2001, Tokyo, Japan, 1/11/01. https://doi.org/10.1109/IWGI.2001.967552

Dual-poly CVD HfO₂ gate stack for sub-100 nm CMOS technology. / Lee, S. J.; Lee, C. H.; Kim, Y. H. et al.
Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001. Institute of Electrical and Electronics Engineers Inc., 2001. p. 80-85 967552 (Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Dual-poly CVD HfO2 gate stack for sub-100 nm CMOS technology

AU - Lee, S. J.

AU - Lee, C. H.

AU - Kim, Y. H.

AU - Luan, H. F.

AU - Bai, W. P.

AU - Jeon, T. S.

AU - Kwong, D. L.

PY - 2001

Y1 - 2001

N2 - In this paper, the materials and processing challenges for the fabrication of high-quality, ultra-thin (EOT<1 nm) dual-poly high-k gate stack for sub-100 nm CMOS technology are reviewed along with recent results on CVD HfO2. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve the thinnest possible EOT (equivalent oxide thickness) is discussed. Results are presented on the thermal stability of high-k materials, and interfacial reactions of high-k/Si and high-k/gate electrode interfaces. We also discuss key factors that govern the conduction and degradation mechanisms in high-k gate stacks. Finally, recent work on metal nitrides as possible gate electrode materials is reviewed and the upper thermal budget limit for such materials is discussed.

AB - In this paper, the materials and processing challenges for the fabrication of high-quality, ultra-thin (EOT<1 nm) dual-poly high-k gate stack for sub-100 nm CMOS technology are reviewed along with recent results on CVD HfO2. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve the thinnest possible EOT (equivalent oxide thickness) is discussed. Results are presented on the thermal stability of high-k materials, and interfacial reactions of high-k/Si and high-k/gate electrode interfaces. We also discuss key factors that govern the conduction and degradation mechanisms in high-k gate stacks. Finally, recent work on metal nitrides as possible gate electrode materials is reviewed and the upper thermal budget limit for such materials is discussed.

UR - https://www.scopus.com/pages/publications/0012054240

U2 - 10.1109/IWGI.2001.967552

DO - 10.1109/IWGI.2001.967552

M3 - Conference contribution

AN - SCOPUS:0012054240

T3 - Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001

SP - 80

EP - 85

BT - Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - International Workshop on Gate Insulator, IWGI 2001

Y2 - 1 November 2001 through 2 November 2001

ER -

Lee SJ, Lee CH, Kim YH, Luan HF, Bai WP, Jeon TS et al. Dual-poly CVD HfO₂ gate stack for sub-100 nm CMOS technology. In Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001. Institute of Electrical and Electronics Engineers Inc. 2001. p. 80-85. 967552. (Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001). doi: 10.1109/IWGI.2001.967552