Design of real-time SIFT feature extraction

A real-time hardware architecture based on scale-invariant feature transform algorithm (SIFT) feature extraction with parallel technology has been introduced in this paper. The proposed parallel hardware architecture could be able to extract feature via a Field-Programmable Gate Array (FPGA) chip efficiently, which provided the real-time performance and the similar accuracy with software implementation. In terms of hardware resource consumption and speed, the original SIFT algorithm has been significantly optimized in the following aspects: 1) Down-sampling has used to replace with up-sampling for purpose of saving the interpolation calculation. Besides, the flexible Gaussian blur value and self-circulation scale space are proposed to simplify the key point detection operation. 2) Optimized key point detection method replaces the original key point detection methods for there won't be other key points in the neighbor 8 pixels in the same scale if a certain pixel were defined as a key point. Compared with the SIFT algorithm implemented in the software, this kind of architecture based on FPGA performance is similar with software methods and realizes the efficient and real-time.