@inproceedings{be119b927fbb46ebad43a21a3a68062f,
title = "Design of configurable digital spike filtering circuits in 130 nm CMOS process",
abstract = "In this paper, configurable digital spike filtering circuits are explored for removing unwanted noise pulses from the signals. The width of the spike to be suppressed from the signal is configurable. The circuits identify and remove both positive and negative spike pulses accurately. The presented circuits are implemented in 130 nm CMOS process. The asynchronous circuits are implemented in fully custom and fully synthesizable techniques which occupy an area of 252 × 323 μm2 and 127 × 127 μm2 and consumes 419 nW and 226 nW of power respectively from 1.2 V supply. The presented synchronous spike filtering circuit is fully synthesizable and it needs only 348 gate counts for its implementation with an area of 68 × 68 μm2. It draws only 83 nA current form supply for its full operation. The circuits are measured extensively and experimental results verify the accuracy of the proposed spike filtering circuits.",
keywords = "Circuit, CMOS, Configurable, Digital, Filter, Glitch, Spikes",
author = "Imran Ali and Huo Yingge and \{Riaz Ur Rehman\}, Muhamamd and Muhammad Asif and Lee, \{Kang Yoon\}",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 17th International Conference on Frontiers of Information Technology, FIT 2019 ; Conference date: 16-12-2019 Through 18-12-2019",
year = "2019",
month = dec,
doi = "10.1109/FIT47737.2019.00060",
language = "English",
series = "Proceedings - 2019 International Conference on Frontiers of Information Technology, FIT 2019",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "284--286",
booktitle = "Proceedings - 2019 International Conference on Frontiers of Information Technology, FIT 2019",
}