TY - GEN
T1 - Design of asynchronous SAR ADC for low power mixed signal applications
AU - Verma, Deeksha
AU - Kang, Hye Yeong
AU - Shehzad, Khuram
AU - Ur Rehman, Muhammad Riaz
AU - Lee, Kang Yoon
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2018/5/29
Y1 - 2018/5/29
N2 - This paper presents a 10-bit, 8 MS/s Asynchronous SAR ADC with supply voltages of 1 V for low power mixed signal applications. The proposed asynchronous ADC consist of a comparator, SAR logic block and two control blocks (positive CDAC and Negative CDAC). The prototype of the proposed Asynchronous SAR ADC is implemented in 55 nm CMOS process technology. It achieves ENOB of 9.765 bit with sampling frequency of 8MS/s, input range of 0.2-0.8 V and power consumption is 0.124 mW.
AB - This paper presents a 10-bit, 8 MS/s Asynchronous SAR ADC with supply voltages of 1 V for low power mixed signal applications. The proposed asynchronous ADC consist of a comparator, SAR logic block and two control blocks (positive CDAC and Negative CDAC). The prototype of the proposed Asynchronous SAR ADC is implemented in 55 nm CMOS process technology. It achieves ENOB of 9.765 bit with sampling frequency of 8MS/s, input range of 0.2-0.8 V and power consumption is 0.124 mW.
KW - Asynchronous SAR ADC
KW - Comparator
KW - Low-power consumption
UR - https://www.scopus.com/pages/publications/85048855579
U2 - 10.1109/ISOCC.2017.8368863
DO - 10.1109/ISOCC.2017.8368863
M3 - Conference contribution
AN - SCOPUS:85048855579
T3 - Proceedings - International SoC Design Conference 2017, ISOCC 2017
SP - 222
EP - 223
BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th International SoC Design Conference, ISOCC 2017
Y2 - 5 November 2017 through 8 November 2017
ER -