Design of a Fault Detection Circuit for One-Time Programmable Memories for Reducing Time

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

As memory becomes more versatile, testing to detect defects becomes important. Defect testing occurs at various stages of the device's lifecycle to ensure proper functionality and to verify that it meets the specifications determined by the customer. Having a circuit built into the circuit itself to detect faults can ensure accurate and reliable behavior, and eliminate the need for special equipment for testing, reducing costs and saving time. Accordingly, this paper proposes a circuit that can quickly and accurately detect faults in One-Time Programmable (OTP) Memory. The work has been implemented on a TSMC 55nm CMOS process and the OTP Memory is a 256X32bits One Time Programmable Device used in the TSMC 55nm process from eMemory Technology Inc.

Original languageEnglish
Title of host publicationICUFN 2023 - 14th International Conference on Ubiquitous and Future Networks
PublisherIEEE Computer Society
Pages894-897
Number of pages4
ISBN (Electronic)9798350335385
DOIs
StatePublished - 2023
Event14th International Conference on Ubiquitous and Future Networks, ICUFN 2023 - Paris, France
Duration: 4 Jul 20237 Jul 2023

Publication series

NameInternational Conference on Ubiquitous and Future Networks, ICUFN
Volume2023-July
ISSN (Print)2165-8528
ISSN (Electronic)2165-8536

Conference

Conference14th International Conference on Ubiquitous and Future Networks, ICUFN 2023
Country/TerritoryFrance
CityParis
Period4/07/237/07/23

Keywords

  • Fault Detection Circuit
  • One-Time Programmable Memories(OTP)
  • Verilog HDL

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