Design of a Clock Doubler Based on Delay-Locked Loop in a 55 nm RF CMOS Process

In this paper, for the wireless network, wearable device, and Internet of Things (IoT) markets, a delay-locked loop (DLL) is used to implement accurate multiplication for a reference clock and the frequency of various applications through an edge combiner (EC). A simpler structure is more sensitive to process, voltage, and temperature (PVT), so DLL complements itself quickly in the feedback system and improves the stability of the final output. The proposed DLL-based multiplier can prevent harmonic lock generation using a first phase canceller (FPC), thus compensating for faster lock time. The circuit is built with a 55 nm CMOS process and has a chip area of 0.0225 mm². The proposed design achieves a total power consumption of 0.48 mW at the 30.72 MHz operating clock frequency, and the clock duty can also operate stably from 15 to 75%.