TY - GEN
T1 - Design of 14-bit Digital Decimation Filter for Transimpedance Amplifier Based Sensor Application
AU - Kumar, Pervesh
AU - Rehman, Muhammad Riaz Ur
AU - Shehzad, Khuram
AU - Kommangunta, Venkatesh
AU - Lee, Kang Yoon
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/11/1
Y1 - 2020/11/1
N2 - In this paper, a design of a 14-bit digital decimation filter for transimpedance amplifier (TIA) based sensor application is presented. TIA is used for detecting very small variations in the current for highly sensitive sensor applications. The output of TIA is digitized by a high-resolution ADC. The Continuous-Time sigma-delta modulator analog-to-digital converters (CT-SDM ADC) offer a high resolution with CIC based digital filter which reduces the overall power consumption. The proposed digital filter design comprised of three integrators, a digitally controlled decimator, three comb filters, and a digital filter controller. It eliminates the use of power hungry multiplier blocks. Filter controller part controls the output data rate and effective resolution of CT-SD ADC. The proposed filter is designed in Verilog HDL and it is implemented on 0.18um CMOS technology. The digital filter output from the chip is processed by LabVIEW for performance evaluation and ENOB of 13.12 bits measured. Also, the output of TIA is digitized and measured the pluses from the photodiode.
AB - In this paper, a design of a 14-bit digital decimation filter for transimpedance amplifier (TIA) based sensor application is presented. TIA is used for detecting very small variations in the current for highly sensitive sensor applications. The output of TIA is digitized by a high-resolution ADC. The Continuous-Time sigma-delta modulator analog-to-digital converters (CT-SDM ADC) offer a high resolution with CIC based digital filter which reduces the overall power consumption. The proposed digital filter design comprised of three integrators, a digitally controlled decimator, three comb filters, and a digital filter controller. It eliminates the use of power hungry multiplier blocks. Filter controller part controls the output data rate and effective resolution of CT-SD ADC. The proposed filter is designed in Verilog HDL and it is implemented on 0.18um CMOS technology. The digital filter output from the chip is processed by LabVIEW for performance evaluation and ENOB of 13.12 bits measured. Also, the output of TIA is digitized and measured the pluses from the photodiode.
KW - ADC
KW - CIC
KW - Digital filter
KW - SDM
KW - VHDL
UR - https://www.scopus.com/pages/publications/85098872888
U2 - 10.1109/ICCE-Asia49877.2020.9276912
DO - 10.1109/ICCE-Asia49877.2020.9276912
M3 - Conference contribution
AN - SCOPUS:85098872888
T3 - 2020 IEEE International Conference on Consumer Electronics - Asia, ICCE-Asia 2020
BT - 2020 IEEE International Conference on Consumer Electronics - Asia, ICCE-Asia 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 IEEE International Conference on Consumer Electronics - Asia, ICCE-Asia 2020
Y2 - 1 November 2020 through 3 November 2020
ER -