Design for Variability: Counter-Doped Source/Drain Epitaxy Pockets in Gate-All-Around FET

One of the obstacles in the evolution from the fin-shaped field-effect transistor (FinFET) to the gate-all-around field-effect transistor (GAAFET) is the etching-depth variation. In the process step for etching the source/drain (S/D) regions, the variation makes the over-etching inevitable to avoid the fatal issue that under-etched region may induces (e.g., two adjacent gates can be connected in the following processes). However, the over-etching goes with the degradation of device performance, especially OFF-state performance. To ease the degradation, a counter-doped pocket was suggested in this work. The process parameters for the pocket such as the over-etching depth (Tov), the pocket epitaxy thickness (TEPI), and the pocket doping concentration (Npocket) were explored. Subsequently, the device performance was evaluated with respect to OFF-state leakage current (IOFF) and threshold voltage (Vth) variation. It was confirmed that the IOFF decreased, and the Vth variation was suppressed with optimized process parameters. By analyzing the total doping concentration at substrate, it also turned out that the GAAFET with the pocket can give advantageous impact on the feasibility.