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Deembedding accuracy for device scale and interconnection line parasitics

  • Jaeho Lee
  • , Jaehong Lee
  • , Jongwook Jeon
  • , Hee Sauk Jhon
  • , Hyungcheol Shin
  • Seoul National University

Research output: Contribution to journal › Article › peer-review

Abstract

In this letter, we investigate the deembedding accuracy of OPEN-SHORT (OS) and PAD-OPEN-SHORT (POS) deembedding for transistor measurement and modeling. It is found that all of the transistor intrinsic element values except for the gate-resistance, Rgare independent of the deembedding procedure. Furthermore, the difference in Rg is dependent on the device size. To analyze the origin of the deembedding difference, the equivalent circuits of the PADs and interconnection lines are constructed from the measured data by varying the values of parasitic parameters.

Original languageEnglish
Article number5290042
Pages (from-to)713-715
Number of pages3
JournalIEEE Microwave and Wireless Components Letters
Volume19
Issue number11
DOIs
StatePublished - Nov 2009
Externally publishedYes

Keywords

  • Deembedding technique
  • Interconnection-line parasitics
  • Open-short (OS)
  • Pad-open-short (POS)
  • R
  • RF CMOS

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