Dedicated parallel thinning architecture based on FPGA

Hoon Kim Ki; Cong Thien Pham; Hun Jin Seung; Kyun Kim Dong; Wook Jeon Jae

doi:10.1109/MFI.2008.4648066

Dedicated parallel thinning architecture based on FPGA

Hoon Kim Ki, Cong Thien Pham, Hun Jin Seung, Kyun Kim Dong, Wook Jeon Jae

Department of Semiconductor Systems Engineering

Sungkyunkwan University

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

Thinning is a widely used image processing method which can extract feature parameters from an image. Because of the time complexity caused by repetitive operations of thinning algorithm, many approaches have been done to obtain real-time performance. However, previous thinning algorithms have several limitations for thinning large volumes of data in the processing time aspect. This paper presents parallel thinning architecture and its FPGA-based implementation which can process thinning in real-time. The proposed system is evaluated using large volumes of real-world data and verified its real-time performance.

Original language	English
Pages	208-213
Number of pages	6
DOIs	https://doi.org/10.1109/MFI.2008.4648066
State	Published - 2008
Event	2008 IEEE International Conference on Multisensor Fusion and Integration for Intelligent Systems, MFI - Seoul, Korea, Republic of Duration: 20 Aug 2008 → 22 Aug 2008

Conference

Conference	2008 IEEE International Conference on Multisensor Fusion and Integration for Intelligent Systems, MFI
Country/Territory	Korea, Republic of
City	Seoul
Period	20/08/08 → 22/08/08

Access to Document

10.1109/MFI.2008.4648066

Cite this

@conference{f1be4a77b8824d77bbbde67d43970982,

title = "Dedicated parallel thinning architecture based on FPGA",

abstract = "Thinning is a widely used image processing method which can extract feature parameters from an image. Because of the time complexity caused by repetitive operations of thinning algorithm, many approaches have been done to obtain real-time performance. However, previous thinning algorithms have several limitations for thinning large volumes of data in the processing time aspect. This paper presents parallel thinning architecture and its FPGA-based implementation which can process thinning in real-time. The proposed system is evaluated using large volumes of real-world data and verified its real-time performance.",

author = "Ki, \{Hoon Kim\} and Pham, \{Cong Thien\} and Seung, \{Hun Jin\} and Dong, \{Kyun Kim\} and Jae, \{Wook Jeon\}",

year = "2008",

doi = "10.1109/MFI.2008.4648066",

language = "English",

pages = "208--213",

note = "2008 IEEE International Conference on Multisensor Fusion and Integration for Intelligent Systems, MFI ; Conference date: 20-08-2008 Through 22-08-2008",

}

TY - CONF

T1 - Dedicated parallel thinning architecture based on FPGA

AU - Ki, Hoon Kim

AU - Pham, Cong Thien

AU - Seung, Hun Jin

AU - Dong, Kyun Kim

AU - Jae, Wook Jeon

PY - 2008

Y1 - 2008

N2 - Thinning is a widely used image processing method which can extract feature parameters from an image. Because of the time complexity caused by repetitive operations of thinning algorithm, many approaches have been done to obtain real-time performance. However, previous thinning algorithms have several limitations for thinning large volumes of data in the processing time aspect. This paper presents parallel thinning architecture and its FPGA-based implementation which can process thinning in real-time. The proposed system is evaluated using large volumes of real-world data and verified its real-time performance.

AB - Thinning is a widely used image processing method which can extract feature parameters from an image. Because of the time complexity caused by repetitive operations of thinning algorithm, many approaches have been done to obtain real-time performance. However, previous thinning algorithms have several limitations for thinning large volumes of data in the processing time aspect. This paper presents parallel thinning architecture and its FPGA-based implementation which can process thinning in real-time. The proposed system is evaluated using large volumes of real-world data and verified its real-time performance.

UR - https://www.scopus.com/pages/publications/67650527577

U2 - 10.1109/MFI.2008.4648066

DO - 10.1109/MFI.2008.4648066

M3 - Paper

AN - SCOPUS:67650527577

SP - 208

EP - 213

T2 - 2008 IEEE International Conference on Multisensor Fusion and Integration for Intelligent Systems, MFI

Y2 - 20 August 2008 through 22 August 2008

ER -

Dedicated parallel thinning architecture based on FPGA

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this