Abstract
Most silicon nano-devices use ion implantation doping for electric characteristics due to precise control of concentration and location of the dopants. A consequence of ion implantation is the damage to the silicon caused when injecting dopants into silicon substrate that break the silicon structure. This damage causes leakage or electron trapping in device circuits. Therefore, minimizing implant damage is of high importance. In general, ion implantation uses photoresist coatings, which can endure no more than 200 °C to make selected area doping. We characterized ion implantation damage on bare wafers by optimizing the process temperature during implant. Elevated temperatures during implant induce “self-annealing” which reduces the damage to the silicon structure as the implant occurs. We propose that in-situ temperature control can limit ion implant damage on the transistor well and photo diode steps on advanced Complementary Metal-Oxide Semiconductor (CMOS) image sensor devices.
| Original language | English |
|---|---|
| Article number | 105164 |
| Journal | Materials Science in Semiconductor Processing |
| Volume | 117 |
| DOIs | |
| State | Published - Oct 2020 |
Keywords
- Implant damage
- Implant defect
- Ion implantation
- Shallow junction