Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay

Jinseok Kim; Yulhwa Kim; Sungho Kim; Jae Joon Kim

doi:10.1145/3218603.3218639

Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay

Jinseok Kim
, Yulhwa Kim
, Sungho Kim
, Jae Joon Kim

Pohang University of Science and Technology
Samsung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Mapping Convolutional Neural Network (CNN) to a neuromorphic hardware has been inefficient in synapse memory usage because both kernel/input reuse are not exploitedwell.We propose a method to enable kernel reuse by utilizing axonal delay, which is a biological parameter for a spiking neuron. Using IBM TrueNorth as a test platform, we demonstrate that the number of cores, neurons, synapses, and synaptic operations per time step can be reduced by up to 20.9×, 27.9×, 88.4×, and 1586×, respectively, compared to the conventional scheme, which raises the possibility of implementing large-scale CNN on neuromorphic hardware.

Original language	English
Title of host publication	ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781450357043
DOIs	https://doi.org/10.1145/3218603.3218639
State	Published - 23 Jul 2018
Externally published	Yes
Event	23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018 - Bellevue, United States Duration: 23 Jul 2018 → 25 Jul 2018

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Conference

Conference	23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018
Country/Territory	United States
City	Bellevue
Period	23/07/18 → 25/07/18

Keywords

Axonal delay
Convolutional neural network
Neuromorphic hardware
Reduced precision network

Access to Document

10.1145/3218603.3218639

Cite this

Kim, J., Kim, Y., Kim, S., & Kim, J. J. (2018). Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay. In ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design Article a3 (Proceedings of the International Symposium on Low Power Electronics and Design). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3218603.3218639

@inproceedings{97bde8ed7ea14fa8b4c477a148a0050d,

title = "Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay",

abstract = "Mapping Convolutional Neural Network (CNN) to a neuromorphic hardware has been inefficient in synapse memory usage because both kernel/input reuse are not exploitedwell.We propose a method to enable kernel reuse by utilizing axonal delay, which is a biological parameter for a spiking neuron. Using IBM TrueNorth as a test platform, we demonstrate that the number of cores, neurons, synapses, and synaptic operations per time step can be reduced by up to 20.9×, 27.9×, 88.4×, and 1586×, respectively, compared to the conventional scheme, which raises the possibility of implementing large-scale CNN on neuromorphic hardware.",

keywords = "Axonal delay, Convolutional neural network, Neuromorphic hardware, Reduced precision network",

author = "Jinseok Kim and Yulhwa Kim and Sungho Kim and Kim, \{Jae Joon\}",

note = "Publisher Copyright: {\textcopyright} 2018 Association for Computing Machinery.; 23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018 ; Conference date: 23-07-2018 Through 25-07-2018",

year = "2018",

month = jul,

day = "23",

doi = "10.1145/3218603.3218639",

language = "English",

isbn = "9781450357043",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design",

}

Kim, J, Kim, Y, Kim, S & Kim, JJ 2018, Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay. in ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design., a3, Proceedings of the International Symposium on Low Power Electronics and Design, Institute of Electrical and Electronics Engineers Inc., 23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018, Bellevue, United States, 23/07/18. https://doi.org/10.1145/3218603.3218639

Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay. / Kim, Jinseok; Kim, Yulhwa; Kim, Sungho et al.
ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2018. a3 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay

AU - Kim, Jinseok

AU - Kim, Yulhwa

AU - Kim, Sungho

AU - Kim, Jae Joon

PY - 2018/7/23

Y1 - 2018/7/23

N2 - Mapping Convolutional Neural Network (CNN) to a neuromorphic hardware has been inefficient in synapse memory usage because both kernel/input reuse are not exploitedwell.We propose a method to enable kernel reuse by utilizing axonal delay, which is a biological parameter for a spiking neuron. Using IBM TrueNorth as a test platform, we demonstrate that the number of cores, neurons, synapses, and synaptic operations per time step can be reduced by up to 20.9×, 27.9×, 88.4×, and 1586×, respectively, compared to the conventional scheme, which raises the possibility of implementing large-scale CNN on neuromorphic hardware.

AB - Mapping Convolutional Neural Network (CNN) to a neuromorphic hardware has been inefficient in synapse memory usage because both kernel/input reuse are not exploitedwell.We propose a method to enable kernel reuse by utilizing axonal delay, which is a biological parameter for a spiking neuron. Using IBM TrueNorth as a test platform, we demonstrate that the number of cores, neurons, synapses, and synaptic operations per time step can be reduced by up to 20.9×, 27.9×, 88.4×, and 1586×, respectively, compared to the conventional scheme, which raises the possibility of implementing large-scale CNN on neuromorphic hardware.

KW - Axonal delay

KW - Convolutional neural network

KW - Neuromorphic hardware

KW - Reduced precision network

UR - https://www.scopus.com/pages/publications/85051459767

U2 - 10.1145/3218603.3218639

DO - 10.1145/3218603.3218639

M3 - Conference contribution

AN - SCOPUS:85051459767

SN - 9781450357043

T3 - Proceedings of the International Symposium on Low Power Electronics and Design

BT - ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018

Y2 - 23 July 2018 through 25 July 2018

ER -

Kim J, Kim Y, Kim S, Kim JJ. Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay. In ISLPED 2018 - Proceedings of the 2018 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc. 2018. a3. (Proceedings of the International Symposium on Low Power Electronics and Design). doi: 10.1145/3218603.3218639

Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay

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Keywords

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