Code-based cache partitioning for improving hardware cache performance

Recently, improving hardware cache performance is getting more important, because the performance gap between processor and memory has caused "memory wall" problem. Most cache designs are based on the LRU replacement policy which is effective for high-locality workloads. However, it is ineffective for the workloads that have a working set greater than available cache size or weak-memory access patterns. To make up for the weakness of LRU policy, we introduce a novel code-based cache partitioning mechanism which does not require any hardware support. In our mechanism, we first collect profile data using binary instrumentation, and then classify the characteristic of code region through the collected code profiles. Finally, while the application is running, page coloring technique is used for code-based cache partitioning. To show effectiveness of our mechanism, we implemented our mechanism in the Linux kernel. Experiments on the workloads including weak-memory access pattern show that the proposed mechanism achieves performance improvement by up to 7.3% and the last-level cache miss reduction by up to 37.8%.