TY - GEN
T1 - CMOS up-conversion mixer with adaptive bias circuit for UHF RFID reader
AU - Choi, Kyonggon
AU - Kim, Minsu
AU - Kim, Hyung Chul
AU - Cho, Hanjin
AU - Cho, Jaeyong
AU - Yoo, Sungchul
AU - Yang, Kyoungon
AU - Jung, Sungchan
AU - Ryu, Sunghan
AU - Yang, Youngoo
PY - 2009
Y1 - 2009
N2 - The paper proposes a new CMOS passive up-conversion mixer with an adaptive bias circuit providing a building block for the transmitter (TX) in UHF RFID reader devices implemented in system-on-chip (SoC) technologies. A high linearity of the passive mixer can be maintained over a wide range of DC levels at the DC-coupled IF signal, using the proposed adaptive bias circuit. The input DC voltage, sensed by the adaptive bias circuit, is shifted to an appropriate level, and supplied to the gates of the switching transistors so that the proper bias level of the switching transistor can be maintained. A CMOS passive mixer with the adaptive bias circuit has been designed and implemented using 0.18um CMOS technology and experimental results have shown that a conversion gain of -3.7dB, an input 1dB compression point (IP1dB) of 9dBm, a high input intercept point (IIP3) of 19dBm, and a double sideband noise figure (DSB NF) of 4dB can be achieved. The measured IIP3 can be maintained over a wide range of input DC voltages.
AB - The paper proposes a new CMOS passive up-conversion mixer with an adaptive bias circuit providing a building block for the transmitter (TX) in UHF RFID reader devices implemented in system-on-chip (SoC) technologies. A high linearity of the passive mixer can be maintained over a wide range of DC levels at the DC-coupled IF signal, using the proposed adaptive bias circuit. The input DC voltage, sensed by the adaptive bias circuit, is shifted to an appropriate level, and supplied to the gates of the switching transistors so that the proper bias level of the switching transistor can be maintained. A CMOS passive mixer with the adaptive bias circuit has been designed and implemented using 0.18um CMOS technology and experimental results have shown that a conversion gain of -3.7dB, an input 1dB compression point (IP1dB) of 9dBm, a high input intercept point (IIP3) of 19dBm, and a double sideband noise figure (DSB NF) of 4dB can be achieved. The measured IIP3 can be maintained over a wide range of input DC voltages.
KW - Adaptive bias circuit
KW - CMOS passive mixer
KW - Input intercept point
KW - UHF RFID reader
KW - Up-conversion mixer
UR - https://www.scopus.com/pages/publications/77951441342
U2 - 10.1109/RFIT.2009.5383697
DO - 10.1109/RFIT.2009.5383697
M3 - Conference contribution
AN - SCOPUS:77951441342
SN - 9781424450312
T3 - 2009 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2009
SP - 20
EP - 23
BT - 2009 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2009
T2 - 2009 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2009
Y2 - 9 January 2009 through 11 January 2009
ER -