CMOS technology: Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode

Shiyang Zhu; H. Y. Yu; S. J. Whang; J. H. Chen; Chen Shen; Chunxiang Zhu; S. J. Lee; M. F. Li; D. S.H. Chan; W. J. Yoo; Anyan Du; C. H. Tung; Jagar Singh; Albert Chin; D. L. Kwong

doi:10.1142/9781848164079_0006

CMOS technology: Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode

Shiyang Zhu
, H. Y. Yu
, S. J. Whang
, J. H. Chen
, Chen Shen
, Chunxiang Zhu
, S. J. Lee
, M. F. Li
, D. S.H. Chan
, W. J. Yoo
, Anyan Du
, C. H. Tung
, Jagar Singh
, Albert Chin
, D. L. Kwong

National University of Singapore
Fudan University
Jusung Engineering Co., Ltd.
Agency for Science, Technology and Research, Singapore
National Yang Ming Chiao Tung University
University of Texas at Austin

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

Abstract

This letter presents a low-tempcrature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-? gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D), excellent electrical performance of I_on/I_off~ 10⁷- 10⁸and subthreshold slope of 66 mV/dec have been achieved. For n-channcl SSDTs (N-SSDTs) using DySi_2-xS/D, Ion/Ioff can reach ~ 10⁵at V_dsof 0.2 V with two subthrcshold slopes of 80 and 340 mV/dec. The low-tcm-perature process relaxes the thermal budget of high-? dielectric and metal-gate materials to be used in the future generation CMOS technology.

Original language	English
Title of host publication	Selected Semiconductor Research
Publisher	Imperial College Press
Pages	330-332
Number of pages	3
ISBN (Electronic)	9781848164079
ISBN (Print)	9781848164062
DOIs	https://doi.org/10.1142/9781848164079_0006
State	Published - 1 Jan 2011
Externally published	Yes

Keywords

High-?
Metal gate
MOSFET
Schottky

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10.1142/9781848164079_0006

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Zhu, S., Yu, H. Y., Whang, S. J., Chen, J. H., Shen, C., Zhu, C., Lee, S. J., Li, M. F., Chan, D. S. H., Yoo, W. J., Du, A., Tung, C. H., Singh, J., Chin, A., & Kwong, D. L. (2011). CMOS technology: Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode. In Selected Semiconductor Research (pp. 330-332). Imperial College Press. https://doi.org/10.1142/9781848164079_0006

@inbook{797b165c31484a8d9cb309653c604cec,

title = "CMOS technology: Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode",

abstract = "This letter presents a low-tempcrature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-? gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D), excellent electrical performance of Ion/Ioff\textasciitilde{} 107- 108and subthreshold slope of 66 mV/dec have been achieved. For n-channcl SSDTs (N-SSDTs) using DySi2-xS/D, Ion/Ioff can reach \textasciitilde{} 105at Vdsof 0.2 V with two subthrcshold slopes of 80 and 340 mV/dec. The low-tcm-perature process relaxes the thermal budget of high-? dielectric and metal-gate materials to be used in the future generation CMOS technology.",

keywords = "High-?, Metal gate, MOSFET, Schottky",

author = "Shiyang Zhu and Yu, \{H. Y.\} and Whang, \{S. J.\} and Chen, \{J. H.\} and Chen Shen and Chunxiang Zhu and Lee, \{S. J.\} and Li, \{M. F.\} and Chan, \{D. S.H.\} and Yoo, \{W. J.\} and Anyan Du and Tung, \{C. H.\} and Jagar Singh and Albert Chin and Kwong, \{D. L.\}",

year = "2011",

month = jan,

day = "1",

doi = "10.1142/9781848164079\_0006",

language = "English",

isbn = "9781848164062",

pages = "330--332",

booktitle = "Selected Semiconductor Research",

publisher = "Imperial College Press",

}

TY - CHAP

T1 - CMOS technology

T2 - Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode

AU - Zhu, Shiyang

AU - Yu, H. Y.

AU - Whang, S. J.

AU - Chen, J. H.

AU - Shen, Chen

AU - Zhu, Chunxiang

AU - Lee, S. J.

AU - Li, M. F.

AU - Chan, D. S.H.

AU - Yoo, W. J.

AU - Du, Anyan

AU - Tung, C. H.

AU - Singh, Jagar

AU - Chin, Albert

AU - Kwong, D. L.

PY - 2011/1/1

Y1 - 2011/1/1

N2 - This letter presents a low-tempcrature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-? gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D), excellent electrical performance of Ion/Ioff~ 107- 108and subthreshold slope of 66 mV/dec have been achieved. For n-channcl SSDTs (N-SSDTs) using DySi2-xS/D, Ion/Ioff can reach ~ 105at Vdsof 0.2 V with two subthrcshold slopes of 80 and 340 mV/dec. The low-tcm-perature process relaxes the thermal budget of high-? dielectric and metal-gate materials to be used in the future generation CMOS technology.

AB - This letter presents a low-tempcrature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-? gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D), excellent electrical performance of Ion/Ioff~ 107- 108and subthreshold slope of 66 mV/dec have been achieved. For n-channcl SSDTs (N-SSDTs) using DySi2-xS/D, Ion/Ioff can reach ~ 105at Vdsof 0.2 V with two subthrcshold slopes of 80 and 340 mV/dec. The low-tcm-perature process relaxes the thermal budget of high-? dielectric and metal-gate materials to be used in the future generation CMOS technology.

KW - High-?

KW - Metal gate

KW - MOSFET

KW - Schottky

UR - https://www.scopus.com/pages/publications/84967395032

U2 - 10.1142/9781848164079_0006

DO - 10.1142/9781848164079_0006

M3 - Chapter

AN - SCOPUS:84967395032

SN - 9781848164062

SP - 330

EP - 332

BT - Selected Semiconductor Research

PB - Imperial College Press

ER -

CMOS technology: Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode

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Keywords

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