TY - GEN
T1 - Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation
AU - Na, Taesik
AU - Ko, Jong Hwan
AU - Mukhopadhyay, Saibal
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/5/11
Y1 - 2017/5/11
N2 - Adaptive clock generation to track critical path delay enables lowering supply voltage with improved timing slack under supply noise. This paper presents how to synthesize clock tree in adaptive clocking to fully exploit the clock data compensation (CDC) effect in digital circuits. The paper first provides analytical proof of ideal CDC effect for ring oscillator based clock generation. Second, the paper analyzes non-ideal CDC effect in a gate dominated critical path and wire dominated clock tree design. The paper shows the delay sensitivity mismatch between clock tree and critical path can degrade CDC effect by analyzing timing slack under power supply noise (PSN). Finally, the paper proposes simple but efficient clock tree synthesis (CTS) technique to maximize timing slack under PSN in digital circuits with adaptive clock generation.
AB - Adaptive clock generation to track critical path delay enables lowering supply voltage with improved timing slack under supply noise. This paper presents how to synthesize clock tree in adaptive clocking to fully exploit the clock data compensation (CDC) effect in digital circuits. The paper first provides analytical proof of ideal CDC effect for ring oscillator based clock generation. Second, the paper analyzes non-ideal CDC effect in a gate dominated critical path and wire dominated clock tree design. The paper shows the delay sensitivity mismatch between clock tree and critical path can degrade CDC effect by analyzing timing slack under power supply noise (PSN). Finally, the paper proposes simple but efficient clock tree synthesis (CTS) technique to maximize timing slack under PSN in digital circuits with adaptive clock generation.
KW - Adaptive clock
KW - Clock data compensation
KW - Clock tree synthesis
UR - https://www.scopus.com/pages/publications/85020221697
U2 - 10.23919/DATE.2017.7927229
DO - 10.23919/DATE.2017.7927229
M3 - Conference contribution
AN - SCOPUS:85020221697
T3 - Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
SP - 1504
EP - 1509
BT - Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th Design, Automation and Test in Europe, DATE 2017
Y2 - 27 March 2017 through 31 March 2017
ER -