Chip level lithography verification system with artificial neural networks

The lithography verification of critical dimension variation, pinching, and bridging becomes indispensable in synthesizing mask data for the photolithography process. In handling IC layout data, the software usually use the hierarchical information of the design to reduce execution time and to overcome peak memory usage. However, the layout data become flattened by resolution enhancement techniques, such as optical proximity correction, assist features insertion, and dummy pattern insertion. Consequently, the lithography verification software should take burden of processing the flattened data. This paper describes the hierarchy restructuring and artificial neural networks methods in developing a rapid lithography verification system. The hierarchy restructuring method is applied on layout patterns so that the lithography verification on the flattened layout data can attain the speed of hierarchical processing. Artificial neural networks are employed to replace lithography simulation. We define input parameters, which is major factors in determining patterns width, for the artificial neural network system. We also introduce a learning technique in the neural networks to achieve accuracy comparable to an existing lithography verification system. Failure detection with artificial neural networks outperforms the methods that use the convolution-based simulation. The proposed system shows 10 times better performance than a widely accepted system while it achieves the same predictability on lithography failures.