Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO₂-SiO₂) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO₂ into the multiple gate dielectric system-on-a-chlp (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5-V operation/tolerance). Results show that CVD HfO₂-SiO₂ stacked gate dielectric (EOT = 6.2 nm) exhibits lower leakage current than that of SiO₂ (EOT = 5.7 nm) by a factor of ∼10², with comparable interface quality (D_it ∼ 1 × 10¹⁰ cm^-2 eV^-1). The presence of negative fixed charge is observed in HfO₂-SiO₂ gate stack. In addition, the addition of HfO₂ on SiO₂ does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in HfO₂-SiO₂ gate stack. Furthermore, the HfO₂-SiO₂ gate stack shows longer time to breakdown T_BD than SiO₂ under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V_t stability (charge trapping under stress) can be met and the negative fixed charge eliminated.