Channel strain measurement of Si_1-xC_x structures: Effects of gate length, source/drain length, and source/drain elevation

This study examined the dimensional effects on the channel strain in transistor structures with epitaxial Si_1-xC_x stressors embedded in the source/drain region using both nanobeam diffraction and finite element simulations. The sizes of the gate and source/drain exerted a strong influence on the channel strain but in opposite directions: While declining linearly with decreasing source/drain length, the channel strain increases at an escalating rate with decreasing gate length. For source/drain elevation, its effects on the channel strain were found to be quite limited to the top surface region; however, this elevation method could be more effective for short-channel transistors.