Centip3De: A cluster-based NTC architecture with 64 ARM cortex-M3 cores in 3D stacked 130 nm CMOS

David Fick; Ronald G. Dreslinski; Bharan Giridhar; Gyouho Kim; Sangwon Seo; Matthew Fojtik; Sudhir Satpathy; Yoonmyung Lee; Daeyeon Kim; Nurrachman Liu; Michael Wieckowski; Gregory Chen; Trevor Mudge; David Blaauw; Dennis Sylvester

doi:10.1109/JSSC.2012.2222814

Centip3De: A cluster-based NTC architecture with 64 ARM cortex-M3 cores in 3D stacked 130 nm CMOS

David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory Chen, Trevor Mudge, David Blaauw, Dennis Sylvester

University of Michigan, Ann Arbor

Research output: Contribution to journal › Article › peer-review

32 Scopus citations

Abstract

We present Centip3De, a large-scale 3D CMP with a cluster-based near-threshold computing (NTC) architecture. Centip3De uses a 3D stacking technology in conjunction with 130 nm CMOS. Measured results for a two-layer, 64-core system are discussed, with the system achieving 3930 DMIPS/W energy efficiency, which is > 3x improvement over traditional operation at full supply voltage. This project demonstrates the feasibility of large-scale 3D design, a synergy between 3D and NTC architectures, a unique cluster-based NTC cache design, and how to maximize performance in a thermally-constrained design.

Original language	English
Article number	6399548
Pages (from-to)	104-117
Number of pages	14
Journal	IEEE Journal of Solid-State Circuits
Volume	48
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2012.2222814
State	Published - 2013
Externally published	Yes

Keywords

3D integrated circuits
energy efficient
many-core architectures
Near-threshold computing
through-silicon vias

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/JSSC.2012.2222814

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Fick, D., Dreslinski, R. G., Giridhar, B., Kim, G., Seo, S., Fojtik, M., Satpathy, S., Lee, Y., Kim, D., Liu, N., Wieckowski, M., Chen, G., Mudge, T., Blaauw, D., & Sylvester, D. (2013). Centip3De: A cluster-based NTC architecture with 64 ARM cortex-M3 cores in 3D stacked 130 nm CMOS. IEEE Journal of Solid-State Circuits, 48(1), 104-117. Article 6399548. https://doi.org/10.1109/JSSC.2012.2222814

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title = "Centip3De: A cluster-based NTC architecture with 64 ARM cortex-M3 cores in 3D stacked 130 nm CMOS",

abstract = "We present Centip3De, a large-scale 3D CMP with a cluster-based near-threshold computing (NTC) architecture. Centip3De uses a 3D stacking technology in conjunction with 130 nm CMOS. Measured results for a two-layer, 64-core system are discussed, with the system achieving 3930 DMIPS/W energy efficiency, which is > 3x improvement over traditional operation at full supply voltage. This project demonstrates the feasibility of large-scale 3D design, a synergy between 3D and NTC architectures, a unique cluster-based NTC cache design, and how to maximize performance in a thermally-constrained design.",

keywords = "3D integrated circuits, energy efficient, many-core architectures, Near-threshold computing, through-silicon vias",

author = "David Fick and Dreslinski, \{Ronald G.\} and Bharan Giridhar and Gyouho Kim and Sangwon Seo and Matthew Fojtik and Sudhir Satpathy and Yoonmyung Lee and Daeyeon Kim and Nurrachman Liu and Michael Wieckowski and Gregory Chen and Trevor Mudge and David Blaauw and Dennis Sylvester",

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doi = "10.1109/JSSC.2012.2222814",

language = "English",

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Fick, D, Dreslinski, RG, Giridhar, B, Kim, G, Seo, S, Fojtik, M, Satpathy, S, Lee, Y, Kim, D, Liu, N, Wieckowski, M, Chen, G, Mudge, T, Blaauw, D & Sylvester, D 2013, 'Centip3De: A cluster-based NTC architecture with 64 ARM cortex-M3 cores in 3D stacked 130 nm CMOS', IEEE Journal of Solid-State Circuits, vol. 48, no. 1, 6399548, pp. 104-117. https://doi.org/10.1109/JSSC.2012.2222814

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T2 - A cluster-based NTC architecture with 64 ARM cortex-M3 cores in 3D stacked 130 nm CMOS

AU - Fick, David

AU - Dreslinski, Ronald G.

AU - Giridhar, Bharan

AU - Kim, Gyouho

AU - Seo, Sangwon

AU - Fojtik, Matthew

AU - Satpathy, Sudhir

AU - Lee, Yoonmyung

AU - Kim, Daeyeon

AU - Liu, Nurrachman

AU - Wieckowski, Michael

AU - Chen, Gregory

AU - Mudge, Trevor

AU - Blaauw, David

AU - Sylvester, Dennis

PY - 2013

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N2 - We present Centip3De, a large-scale 3D CMP with a cluster-based near-threshold computing (NTC) architecture. Centip3De uses a 3D stacking technology in conjunction with 130 nm CMOS. Measured results for a two-layer, 64-core system are discussed, with the system achieving 3930 DMIPS/W energy efficiency, which is > 3x improvement over traditional operation at full supply voltage. This project demonstrates the feasibility of large-scale 3D design, a synergy between 3D and NTC architectures, a unique cluster-based NTC cache design, and how to maximize performance in a thermally-constrained design.

AB - We present Centip3De, a large-scale 3D CMP with a cluster-based near-threshold computing (NTC) architecture. Centip3De uses a 3D stacking technology in conjunction with 130 nm CMOS. Measured results for a two-layer, 64-core system are discussed, with the system achieving 3930 DMIPS/W energy efficiency, which is > 3x improvement over traditional operation at full supply voltage. This project demonstrates the feasibility of large-scale 3D design, a synergy between 3D and NTC architectures, a unique cluster-based NTC cache design, and how to maximize performance in a thermally-constrained design.

KW - 3D integrated circuits

KW - energy efficient

KW - many-core architectures

KW - Near-threshold computing

KW - through-silicon vias

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IS - 1

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ER -

Centip3De: A cluster-based NTC architecture with 64 ARM cortex-M3 cores in 3D stacked 130 nm CMOS

Abstract

Keywords

UN SDGs

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