Centip3De: A 64-core, 3D stacked, near-threshold system

  • Ronald G. Dreslinski
  • , David Fick
  • , Bharan Giridhar
  • , Gyouho Kim
  • , Sangwon Seo
  • , Matthew Fojtik
  • , Sudhir Satpathy
  • , Yoonmyung Lee
  • , Daeyeon Kim
  • , Nurrachman Liu
  • , Michael Wieckowski
  • , Gregory Chen
  • , Trevor Mudge
  • , Dennis Sylvester
  • , David Blaauw

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This article consists of a collection of slides from the author's conference presentation on Centip3De, a 64-core, three dimensional (3D) stacked near-threshold system. Some of the specific topics discussed include: power management considerations with processor performance; threshold computing and design; architectural impact of near threshold computing (NTC) versis large scale 3D CMP; NTC architectures; cache timing analysis; system specifications and design of the Centip3De system; and an evaluation of 2-layer stacking processing.

Original languageEnglish
Title of host publication2012 IEEE Hot Chips 24 Symposium, HCS 2012
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467388795
DOIs
StatePublished - 20 May 2016
Externally publishedYes
Event24th IEEE Hot Chips Symposium, HCS 2012 - Cupertino, United States
Duration: 27 Aug 201229 Aug 2012

Publication series

Name2012 IEEE Hot Chips 24 Symposium, HCS 2012

Conference

Conference24th IEEE Hot Chips Symposium, HCS 2012
Country/TerritoryUnited States
CityCupertino
Period27/08/1229/08/12

Fingerprint

Dive into the research topics of 'Centip3De: A 64-core, 3D stacked, near-threshold system'. Together they form a unique fingerprint.

Cite this