TY - GEN
T1 - Centip3De
T2 - 59th International Solid-State Circuits Conference, ISSCC 2012
AU - Fick, David
AU - Dreslinski, Ronald G.
AU - Giridhar, Bharan
AU - Kim, Gyouho
AU - Seo, Sangwon
AU - Fojtik, Matthew
AU - Satpathy, Sudhir
AU - Lee, Yoonmyung
AU - Kim, Daeyeon
AU - Liu, Nurrachman
AU - Wieckowski, Michael
AU - Chen, Gregory
AU - Mudge, Trevor
AU - Sylvester, Dennis
AU - Blaauw, David
PY - 2012
Y1 - 2012
N2 - Recent high performance IC design has been dominated by power density constraints. 3D integration increases device density even further, and these devices will not be usable without viable strategies to reduce power consumption. This paper proposes the use of near-threshold computing (NTC) to address this issue in a stacked 3D system. In NTC, cores are operated near the threshold voltage (∼200mV above Vth) to optimally balance power and performance [1]. In Centip3De, we operate cores at 650mV, as opposed to the wear-out limited supply voltage of 1.5V. This improves measured energy efficiency by 5.1x. The dramatically lower power consumption of NTC makes it an attractive match for 3D design, which has limited power dissipation capabilities, but also has improved innate power and performance compared to 2D design.
AB - Recent high performance IC design has been dominated by power density constraints. 3D integration increases device density even further, and these devices will not be usable without viable strategies to reduce power consumption. This paper proposes the use of near-threshold computing (NTC) to address this issue in a stacked 3D system. In NTC, cores are operated near the threshold voltage (∼200mV above Vth) to optimally balance power and performance [1]. In Centip3De, we operate cores at 650mV, as opposed to the wear-out limited supply voltage of 1.5V. This improves measured energy efficiency by 5.1x. The dramatically lower power consumption of NTC makes it an attractive match for 3D design, which has limited power dissipation capabilities, but also has improved innate power and performance compared to 2D design.
UR - https://www.scopus.com/pages/publications/84860678550
U2 - 10.1109/ISSCC.2012.6176970
DO - 10.1109/ISSCC.2012.6176970
M3 - Conference contribution
AN - SCOPUS:84860678550
SN - 9781467303736
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 190
EP - 191
BT - 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers
Y2 - 19 February 2012 through 23 February 2012
ER -
