TY - GEN
T1 - C-AFA
T2 - 21st International System-on-Chip Design Conference, ISOCC 2024
AU - Park, Juhong
AU - Ko, Jong Hwan
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Digital compute-in-memory (DCIM) architectures are becoming crucial for real-time and accurate deep neural network (DNN) inference due to their capacity for precise computations. However, traditional DCIM systems often struggle to balance precise data processing with computational efficiency. In scenarios where exact computations are not always necessary, especially in DNNs featuring sparse data, existing multi-bit operations frequently fail to achieve an ideal balance between accuracy and efficiency. In this paper, we introduce a novel approach to DCIM architecture that selectively skips computations by using probabilistically determined values, effectively reducing the computational load. Our simulation results demonstrate that this method significantly reduces computing cycles, achieving a speedup of up to 1.5× compared to traditional methods, while maintaining accuracy with only a minimal decrease of 1.5%.
AB - Digital compute-in-memory (DCIM) architectures are becoming crucial for real-time and accurate deep neural network (DNN) inference due to their capacity for precise computations. However, traditional DCIM systems often struggle to balance precise data processing with computational efficiency. In scenarios where exact computations are not always necessary, especially in DNNs featuring sparse data, existing multi-bit operations frequently fail to achieve an ideal balance between accuracy and efficiency. In this paper, we introduce a novel approach to DCIM architecture that selectively skips computations by using probabilistically determined values, effectively reducing the computational load. Our simulation results demonstrate that this method significantly reduces computing cycles, achieving a speedup of up to 1.5× compared to traditional methods, while maintaining accuracy with only a minimal decrease of 1.5%.
KW - approximate full adder (AFA)
KW - deep neural network (DNN)
KW - digital CIM (DCIM)
UR - https://www.scopus.com/pages/publications/85213354096
U2 - 10.1109/ISOCC62682.2024.10762580
DO - 10.1109/ISOCC62682.2024.10762580
M3 - Conference contribution
AN - SCOPUS:85213354096
T3 - Proceedings - International SoC Design Conference 2024, ISOCC 2024
SP - 382
EP - 383
BT - Proceedings - International SoC Design Conference 2024, ISOCC 2024
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 19 August 2024 through 22 August 2024
ER -