Blind correction of gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter: Experimental verification

Munkyo Seo; Mark J.W. Rodwell; Upamanyu Madhow

Blind correction of gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter: Experimental verification

Munkyo Seo
, Mark J.W. Rodwell
, Upamanyu Madhow

University of California at Santa Barbara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

15 Scopus citations

Abstract

We report experimental verification of the previously proposed blind method of correcting gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter (TIADC). The experimental setup allows for two different M=2 TIADC configurations with 14-bit resolution and 200-MHz overall sampling rates. Mismatch parameters are estimated by the blind algorithm with representative narrowband and wideband signals. The spurious-free dynamic range (SFDR) performance is then evaluated by using sinusoids. We discuss performance gain, as well as the limitations of the proposed blind algorithm when applied to real world analog-to-digital (A/D) converters.

Original language	English
Title of host publication	ISCAS 2006
Subtitle of host publication	2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages	3394-3397
Number of pages	4
State	Published - 2006
Externally published	Yes
Event	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: 21 May 2006 → 24 May 2006

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/Territory	Greece
City	Kos
Period	21/05/06 → 24/05/06

Cite this

Seo, M., Rodwell, M. J. W., & Madhow, U. (2006). Blind correction of gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter: Experimental verification. In ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings (pp. 3394-3397). Article 1693354 (Proceedings - IEEE International Symposium on Circuits and Systems).

@inproceedings{f97b408aa60a492a826959c6d6fab9e3,

title = "Blind correction of gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter: Experimental verification",

abstract = "We report experimental verification of the previously proposed blind method of correcting gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter (TIADC). The experimental setup allows for two different M=2 TIADC configurations with 14-bit resolution and 200-MHz overall sampling rates. Mismatch parameters are estimated by the blind algorithm with representative narrowband and wideband signals. The spurious-free dynamic range (SFDR) performance is then evaluated by using sinusoids. We discuss performance gain, as well as the limitations of the proposed blind algorithm when applied to real world analog-to-digital (A/D) converters.",

author = "Munkyo Seo and Rodwell, \{Mark J.W.\} and Upamanyu Madhow",

year = "2006",

language = "English",

isbn = "0780393902",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "3394--3397",

booktitle = "ISCAS 2006",

note = "ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems ; Conference date: 21-05-2006 Through 24-05-2006",

}

Seo, M, Rodwell, MJW & Madhow, U 2006, Blind correction of gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter: Experimental verification. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693354, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 3394-3397, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 21/05/06.

Blind correction of gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter: Experimental verification. / Seo, Munkyo; Rodwell, Mark J.W.; Madhow, Upamanyu.
ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 3394-3397 1693354 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems

AU - Seo, Munkyo

AU - Rodwell, Mark J.W.

AU - Madhow, Upamanyu

PY - 2006

Y1 - 2006

N2 - We report experimental verification of the previously proposed blind method of correcting gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter (TIADC). The experimental setup allows for two different M=2 TIADC configurations with 14-bit resolution and 200-MHz overall sampling rates. Mismatch parameters are estimated by the blind algorithm with representative narrowband and wideband signals. The spurious-free dynamic range (SFDR) performance is then evaluated by using sinusoids. We discuss performance gain, as well as the limitations of the proposed blind algorithm when applied to real world analog-to-digital (A/D) converters.

AB - We report experimental verification of the previously proposed blind method of correcting gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter (TIADC). The experimental setup allows for two different M=2 TIADC configurations with 14-bit resolution and 200-MHz overall sampling rates. Mismatch parameters are estimated by the blind algorithm with representative narrowband and wideband signals. The spurious-free dynamic range (SFDR) performance is then evaluated by using sinusoids. We discuss performance gain, as well as the limitations of the proposed blind algorithm when applied to real world analog-to-digital (A/D) converters.

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M3 - Conference contribution

AN - SCOPUS:34547337734

SN - 0780393902

SN - 9780780393905

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 3394

EP - 3397

BT - ISCAS 2006

Y2 - 21 May 2006 through 24 May 2006

ER -

Blind correction of gain and timing mismatches for a two-channel time-interleaved analog-to-digital converter: Experimental verification

Abstract

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Conference

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