ASMD with duty cycle correction scheme for high-speed DRAM

An analogue synchronous mirror delay with duty cycle correction scheme (ASMDCC), to improve the data transmission performance between DRAM and system, is proposed. The ASMDCC achieves duty cycle correction and clock synchronisation at once within two clock cycles, by using a half value current source. The simulation results show the duty cycle of the internal clock is stabilised with less than ±100 ps deviation from 50% for the wide duty cycle range.