ASMD with duty cycle correction scheme for high-speed DRAM

Seong Jin Jang; Young Hyun Jun; Jae Goo Lee; Bai Sun Kong

doi:10.1049/el:20010717

ASMD with duty cycle correction scheme for high-speed DRAM

Seong Jin Jang, Young Hyun Jun, Jae Goo Lee, Bai Sun Kong

Research output: Contribution to journal › Article › peer-review

9 Scopus citations

Abstract

An analogue synchronous mirror delay with duty cycle correction scheme (ASMDCC), to improve the data transmission performance between DRAM and system, is proposed. The ASMDCC achieves duty cycle correction and clock synchronisation at once within two clock cycles, by using a half value current source. The simulation results show the duty cycle of the internal clock is stabilised with less than ±100 ps deviation from 50% for the wide duty cycle range.

Original language	English
Pages (from-to)	1004-1006
Number of pages	3
Journal	Electronics Letters
Volume	37
Issue number	16
DOIs	https://doi.org/10.1049/el:20010717
State	Published - 2 Aug 2001
Externally published	Yes

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10.1049/el:20010717

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title = "ASMD with duty cycle correction scheme for high-speed DRAM",

abstract = "An analogue synchronous mirror delay with duty cycle correction scheme (ASMDCC), to improve the data transmission performance between DRAM and system, is proposed. The ASMDCC achieves duty cycle correction and clock synchronisation at once within two clock cycles, by using a half value current source. The simulation results show the duty cycle of the internal clock is stabilised with less than ±100 ps deviation from 50\% for the wide duty cycle range.",

author = "Jang, \{Seong Jin\} and Jun, \{Young Hyun\} and Lee, \{Jae Goo\} and Kong, \{Bai Sun\}",

year = "2001",

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doi = "10.1049/el:20010717",

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T1 - ASMD with duty cycle correction scheme for high-speed DRAM

AU - Jang, Seong Jin

AU - Jun, Young Hyun

AU - Lee, Jae Goo

AU - Kong, Bai Sun

PY - 2001/8/2

Y1 - 2001/8/2

N2 - An analogue synchronous mirror delay with duty cycle correction scheme (ASMDCC), to improve the data transmission performance between DRAM and system, is proposed. The ASMDCC achieves duty cycle correction and clock synchronisation at once within two clock cycles, by using a half value current source. The simulation results show the duty cycle of the internal clock is stabilised with less than ±100 ps deviation from 50% for the wide duty cycle range.

AB - An analogue synchronous mirror delay with duty cycle correction scheme (ASMDCC), to improve the data transmission performance between DRAM and system, is proposed. The ASMDCC achieves duty cycle correction and clock synchronisation at once within two clock cycles, by using a half value current source. The simulation results show the duty cycle of the internal clock is stabilised with less than ±100 ps deviation from 50% for the wide duty cycle range.

UR - https://www.scopus.com/pages/publications/0035797458

U2 - 10.1049/el:20010717

DO - 10.1049/el:20010717

M3 - Article

AN - SCOPUS:0035797458

SN - 0013-5194

VL - 37

SP - 1004

EP - 1006

JO - Electronics Letters

JF - Electronics Letters

IS - 16

ER -

ASMD with duty cycle correction scheme for high-speed DRAM

Abstract

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