@inproceedings{9f82e0d9a8eb405991a2f6614c24df71,
title = "Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array",
abstract = "We introduce a SRAM-based binary neural network (BNN) hardware which uses a single 6T SRAM cell for XNOR operation for the first time. The cell is 45\% smaller than the previous 8T bitcell for XNOR operation. We also propose an in-memory calibration and batch normalization to achieve more reliable operation under the presence of process variation.",
author = "Jinseok Kim and Jongeun Koo and Taesu Kim and Yulhwa Kim and Hyungjun Kim and Seunghyun Yoo and Kim, \{Jae Joon\}",
note = "Publisher Copyright: {\textcopyright} 2019 JSAP.; 33rd Symposium on VLSI Circuits, VLSI Circuits 2019 ; Conference date: 09-06-2019 Through 14-06-2019",
year = "2019",
month = jun,
doi = "10.23919/VLSIC.2019.8778160",
language = "English",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "C118--C119",
booktitle = "2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers",
}