Analysis of Electrothermal Characteristics of GAA Vertical Nanoplate-Shaped FETs

Dokyun Son; Ilho Myeong; Hyunsuk Kim; Myounggon Kang; Jongwook Jeon; Hyungcheol Shin

doi:10.1109/TED.2018.2832239

Analysis of Electrothermal Characteristics of GAA Vertical Nanoplate-Shaped FETs

Dokyun Son
, Ilho Myeong
, Hyunsuk Kim
, Myounggon Kang
, Jongwook Jeon
, Hyungcheol Shin

Seoul National University
Korea National University of Transportation
Konkuk University

Research output: Contribution to journal › Article › peer-review

21 Scopus citations

Abstract

In this paper, the thermal and electrical characteristics of a gate-all-around (GAA) vertical nanoplate-shaped field-effect transistor (v_NPFET) are studied for sub-5-nm technologies using well-calibrated technology computer-aided design simulations. An asymmetric structure of a vertical device has different characteristics that depend on the source/drain position. When the source and the drain are placed at the top and the bottom electrodes, respectively, the GAA-v_NPFET drive current increases, but the self-heating effect becomes worse. To co-optimize the performance and the reliability, the gate delay (τ_delay) and the thermal resistance (R^th) were evaluated simultaneously in terms of various geometric factors for the first time, showing that a reckless scaling of the channel thickness below 5 nm significantly degrades the electrothermal characteristics.

Original language	English
Pages (from-to)	3061-3064
Number of pages	4
Journal	IEEE Transactions on Electron Devices
Volume	65
Issue number	7
DOIs	https://doi.org/10.1109/TED.2018.2832239
State	Published - Jul 2018
Externally published	Yes

Keywords

Gate all around (GAA)
gate delay (t delay)
nanoplate
self-heating effect (SHE)
technology computeraided design (TCAD)
vertical device

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10.1109/TED.2018.2832239

Cite this

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title = "Analysis of Electrothermal Characteristics of GAA Vertical Nanoplate-Shaped FETs",

abstract = "In this paper, the thermal and electrical characteristics of a gate-all-around (GAA) vertical nanoplate-shaped field-effect transistor (vNPFET) are studied for sub-5-nm technologies using well-calibrated technology computer-aided design simulations. An asymmetric structure of a vertical device has different characteristics that depend on the source/drain position. When the source and the drain are placed at the top and the bottom electrodes, respectively, the GAA-vNPFET drive current increases, but the self-heating effect becomes worse. To co-optimize the performance and the reliability, the gate delay (τdelay) and the thermal resistance (Rth) were evaluated simultaneously in terms of various geometric factors for the first time, showing that a reckless scaling of the channel thickness below 5 nm significantly degrades the electrothermal characteristics.",

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author = "Dokyun Son and Ilho Myeong and Hyunsuk Kim and Myounggon Kang and Jongwook Jeon and Hyungcheol Shin",

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AU - Son, Dokyun

AU - Myeong, Ilho

AU - Kim, Hyunsuk

AU - Kang, Myounggon

AU - Jeon, Jongwook

AU - Shin, Hyungcheol

PY - 2018/7

Y1 - 2018/7

N2 - In this paper, the thermal and electrical characteristics of a gate-all-around (GAA) vertical nanoplate-shaped field-effect transistor (vNPFET) are studied for sub-5-nm technologies using well-calibrated technology computer-aided design simulations. An asymmetric structure of a vertical device has different characteristics that depend on the source/drain position. When the source and the drain are placed at the top and the bottom electrodes, respectively, the GAA-vNPFET drive current increases, but the self-heating effect becomes worse. To co-optimize the performance and the reliability, the gate delay (τdelay) and the thermal resistance (Rth) were evaluated simultaneously in terms of various geometric factors for the first time, showing that a reckless scaling of the channel thickness below 5 nm significantly degrades the electrothermal characteristics.

AB - In this paper, the thermal and electrical characteristics of a gate-all-around (GAA) vertical nanoplate-shaped field-effect transistor (vNPFET) are studied for sub-5-nm technologies using well-calibrated technology computer-aided design simulations. An asymmetric structure of a vertical device has different characteristics that depend on the source/drain position. When the source and the drain are placed at the top and the bottom electrodes, respectively, the GAA-vNPFET drive current increases, but the self-heating effect becomes worse. To co-optimize the performance and the reliability, the gate delay (τdelay) and the thermal resistance (Rth) were evaluated simultaneously in terms of various geometric factors for the first time, showing that a reckless scaling of the channel thickness below 5 nm significantly degrades the electrothermal characteristics.

KW - Gate all around (GAA)

KW - gate delay (t delay)

KW - nanoplate

KW - self-heating effect (SHE)

KW - technology computeraided design (TCAD)

KW - vertical device

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ER -

Analysis of Electrothermal Characteristics of GAA Vertical Nanoplate-Shaped FETs

Abstract

Keywords

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