TY - GEN
T1 - An Improved Dynamic Latch Comparator with Low Power Consumption for SAR ADC Applications
AU - Mounika, Phanidarapu
AU - Verma, Deeksha
AU - Lee, Kang Yoon
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This paper presents the design of dynamic latch comparator with Adaptive Power Control (APC) technique to have low power consumption for SAR analog-to-digital converter ADC. The proposed comparator consists of a pre-amplifier, latch, and APC structure which helps to reduce the power consumption in the comparator. The proposed comparator achieves a dynamic performance of 61μ V offset, 121ps propagation delay, and 856μ W power consumption at 480MHz frequency with 1. 5V power supply. The developed comparator uses a 130nm CMOS process technology.
AB - This paper presents the design of dynamic latch comparator with Adaptive Power Control (APC) technique to have low power consumption for SAR analog-to-digital converter ADC. The proposed comparator consists of a pre-amplifier, latch, and APC structure which helps to reduce the power consumption in the comparator. The proposed comparator achieves a dynamic performance of 61μ V offset, 121ps propagation delay, and 856μ W power consumption at 480MHz frequency with 1. 5V power supply. The developed comparator uses a 130nm CMOS process technology.
KW - Adaptive Power Control
KW - Dynamic Latch Comparator
KW - low power consumption
KW - Successive Approximation Register
UR - https://www.scopus.com/pages/publications/85148418827
U2 - 10.1109/ISOCC56007.2022.10031425
DO - 10.1109/ISOCC56007.2022.10031425
M3 - Conference contribution
AN - SCOPUS:85148418827
T3 - Proceedings - International SoC Design Conference 2022, ISOCC 2022
SP - 43
EP - 44
BT - Proceedings - International SoC Design Conference 2022, ISOCC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 19th International System-on-Chip Design Conference, ISOCC 2022
Y2 - 19 October 2022 through 22 October 2022
ER -