TY - GEN
T1 - An Energy Efficient Sorting Architecture with Cell-Gating for Top-K Sorting on FPGA
AU - Sol, Jaehyeon
AU - Kim, Yongsoo
AU - Hwang, Chanwook
AU - Ko, Jong Hwan
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Top- K Sorting is a widely used technique for se-lecting the largest or smallest numbers from input elements. In this paper, we present an efficient low-power and flexible top-K sorting architecture with cell gating on field-programmable gate arrays (FPGAs). Our architecture consists of a data filter unit, cell counter, and L-cascaded sorting cells, where the filter unit allows users to select the user-defined data values to sort, the cell counter allows cell gating by counting the number of working cells, and the sorting cells allow sorting with low power and flexible K length with cell gating. The proposed sorting cells update incoming data continuously. In addition, cell gating is introduced to increase the flexibility of top- K length and energy efficiency by turning cells on and off. Our implementation achieves remarkable results with a power consumption of only 0.3W with L=128 and 200MHz on a Xilinx XCKU115 FPGA. Overall, our work contributes to advancing the state of the art in efficient and flexible K sorting on FPG As.
AB - Top- K Sorting is a widely used technique for se-lecting the largest or smallest numbers from input elements. In this paper, we present an efficient low-power and flexible top-K sorting architecture with cell gating on field-programmable gate arrays (FPGAs). Our architecture consists of a data filter unit, cell counter, and L-cascaded sorting cells, where the filter unit allows users to select the user-defined data values to sort, the cell counter allows cell gating by counting the number of working cells, and the sorting cells allow sorting with low power and flexible K length with cell gating. The proposed sorting cells update incoming data continuously. In addition, cell gating is introduced to increase the flexibility of top- K length and energy efficiency by turning cells on and off. Our implementation achieves remarkable results with a power consumption of only 0.3W with L=128 and 200MHz on a Xilinx XCKU115 FPGA. Overall, our work contributes to advancing the state of the art in efficient and flexible K sorting on FPG As.
KW - Field programmable gate array (FPGA)
KW - Flexibility
KW - Low power
KW - Sorting architecture
UR - https://www.scopus.com/pages/publications/85185369585
U2 - 10.1109/MWSCAS57524.2023.10406121
DO - 10.1109/MWSCAS57524.2023.10406121
M3 - Conference contribution
AN - SCOPUS:85185369585
T3 - Midwest Symposium on Circuits and Systems
SP - 501
EP - 505
BT - 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023
Y2 - 6 August 2023 through 9 August 2023
ER -