@inproceedings{c9e283010c994d9aa2a349f2b71b6253,
title = "An Efficient Systolic Array with Variable Data Precision and Dimension Support",
abstract = "Systolic array (SA) architectures have been widely employed in deep learning accelerators with their high computation efficiency. However, the fixed SA structure leads to inefficiency in performance and power when computing variable input dimension and precision. To resolve this drawback, this work proposes a flexible systolic array architecture with variable data precision and dimension (PD-FSA) that can compute variable layers with less computing cycles. By calculating the minimum cycles required for input layers, the proposed architecture can avoid unnecessary computing cycles. We also propose to control the precision according to the layer dimension for reduced computing cycles. The experimental result shows that the proposed PD-FSA achieves up to about 2.9× reduction in the computing cycles.",
keywords = "CNN, Deep Learning, Hardware Accelerator, Systolic array",
author = "Jaehyeon So and Ko, \{Jong Hwan\}",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 19th International System-on-Chip Design Conference, ISOCC 2022 ; Conference date: 19-10-2022 Through 22-10-2022",
year = "2022",
doi = "10.1109/ISOCC56007.2022.10031594",
language = "English",
series = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "257--258",
booktitle = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",
}