An Efficient On-Chip Reference Search and Optimization Algorithms for Variation-Tolerant STT-MRAM Read

A novel reference search algorithm is proposed in this paper to significantly reduce the reference search time of embedded spin transfer torque magnetic random access memory (STT-MRAM). Unlike conventional methods that sequentially search reference levels with linearly increasing references the proposed Dual Read Reference Search (DRRS) algorithm requires only two array read operations. By analyzing the statistical characteristics of the read data using a customized function the optimal reference level can be quickly determined in a few steps. Consequently the number of read operations required for a reference search is reduced providing a substantial improvement in the reference search time. The DRRS algorithm can be operated on-chip its effectiveness was confirmed through simulations. The optimization speed was improved by 85% compared to the conventional methods. Additionally an Triple Read Reference Search (TRRS) algorithm is proposed to decrease the variation occurring across different cell arrays and to enhance optimization accuracy. STT-MRAM is composed of numerous cell arrays where the cell distributions in each array exhibit different characteristics. The TRRS algorithm enhances optimization accuracy for variations occurring in each array achieving over a 2x increase in accuracy compared to the DRRS algorithm. Furthermore Simultaneous Reference Search for P and AP (SRS) algorithm that significantly reduces the search time by simultaneously optimizing Parallel (P) and Anti-parallel state (AP) reference cells is also proposed. Lastly regarding cell degradation after power-up we enable prompt re-optimization through revolutionary time-saving algorithms (DRRS TRRS and SRS). This allows for rapid re-optimization in the event of errors caused by cell degradation and ensures regular optimization to maintain maximum read margin even before errors occur thereby enhancing reliability.