Adaptive program verify scheme for improving NAND flash memory performance and lifespan

Since NAND flash memory program/erase (PE) cycling gradually degrades the reliability of memory cells, the redundancy of error-correction code (ECC) is determined so as to sufficiently ensure the PE cycling endurance at the end of memory lifetime. Therefore, ECC redundancy is under-utilized when PE cycling number is relatively small at the early lifetime. Considering the variations on program speed and error rate depending on the program step pulse voltage (ΔV_PP) in the incremental step pulse programming (ISPP), an adaptive ΔV_PP scheme was proposed in order to improve program performance by exploiting the under-utilized ECC. However, the adaptive ΔV_PP scheme missed the problem of increased voltage stress on memory cells at a large ΔV_PP. The voltage stress will shorten the lifespan of flash memory devices. This paper proposes an adaptive V _verify scheme, which trades the under-utilized ECC for improving program performance at the early lifetime of flash memory without decreasing the memory lifetime. The experiments with real NAND flash chips demonstrate up to 21% of program time improvement and 10% of lifetime improvement over the fixed V_verify scheme.