Accurate BEOL statistical modeling methodology with circuit-level multi-layer process variations

As technology scales down, the impact of BEOL (Back-end of Line) interconnect resistance (R) and capacitance (C) on speed and power of digital circuits have been ever-increasing. Furthermore, in 3-D structured transistors, such as FinFETs and Nano-wire FETs, the parasitic R & C of MOL (Middle of Line) have larger impact on performance and power of the products. Hence, analysis of impact on variations of BEOL and MOL on parasitic component change is necessary. The conventional interconnect corner model uses extreme BEOL variations. However, the possibility of such extreme conditions occurring is stochastically very rare. Therefore, tightened corner models were proposed in order to reduce excessiveness in corner simulations. But this tightened corner models still have excessive ranges because each layer is statistically analyzed separately. In this study, we propose a circuit-level multi-layers aware BEOL corner (CMBC) based on Monte Carlo (MC) simulation of ring-oscillator circuits. This modeling methodology takes into account of both MOL process variations and multi-BEOL layers. As a result, the proposed corner model has a tighter distribution ranges of R & C. Therefore the proposed model allows circuit designers to reduce unnecessary efforts.