A wafer map yield model based on deep learning for wafer productivity enhancement

Sung Ju Jang; Jee Hyong Lee; Tae Woo Kim; Jong Seong Kim; Hyun Jin Lee; Jong Bae Lee

doi:10.1109/ASMC.2018.8373137

A wafer map yield model based on deep learning for wafer productivity enhancement

Sung Ju Jang
, Jee Hyong Lee
, Tae Woo Kim
, Jong Seong Kim
, Hyun Jin Lee
, Jong Bae Lee

Department of Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

In semiconductor manufacturing, evaluating the productivity of wafer maps prior to fabrication for designing an optimal wafer map is one of the most effective solutions for enhancing productivity. However, a yield prediction model is required to accurately evaluate the productivity of wafer maps since the design of a wafer map affects yield. In this paper, we propose a novel yield prediction model based on deep learning algorithms. Our approach exploits spatial relationships among positions of dies, sizes of dies, and die-level yield variations collected from a wafer test. By modeling these spatial features, the accuracy of yield prediction significantly increased. Furthermore, experimental results showed that the proposed yield model and approach help to design a wafer map with higher productivity nearly 13%.

Original language	English
Title of host publication	2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	29-34
Number of pages	6
ISBN (Electronic)	9781538637487
DOIs	https://doi.org/10.1109/ASMC.2018.8373137
State	Published - 5 Jun 2018
Event	29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018 - Saratoga Springs, United States Duration: 30 Apr 2018 → 3 May 2018

Publication series

Name	2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018

Conference

Conference	29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018
Country/Territory	United States
City	Saratoga Springs
Period	30/04/18 → 3/05/18

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

Keywords

Deep learning
Semiconductor manufacturing
Wafer map
Wafer productivity
Yield modeling

Access to Document

10.1109/ASMC.2018.8373137

Cite this

Jang, S. J., Lee, J. H., Kim, T. W., Kim, J. S., Lee, H. J., & Lee, J. B. (2018). A wafer map yield model based on deep learning for wafer productivity enhancement. In 2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018 (pp. 29-34). (2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASMC.2018.8373137

Jang, Sung Ju ; Lee, Jee Hyong ; Kim, Tae Woo et al. / A wafer map yield model based on deep learning for wafer productivity enhancement. 2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 29-34 (2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018).

@inproceedings{180bba6dbe86425981ef28becb3c9f76,

title = "A wafer map yield model based on deep learning for wafer productivity enhancement",

abstract = "In semiconductor manufacturing, evaluating the productivity of wafer maps prior to fabrication for designing an optimal wafer map is one of the most effective solutions for enhancing productivity. However, a yield prediction model is required to accurately evaluate the productivity of wafer maps since the design of a wafer map affects yield. In this paper, we propose a novel yield prediction model based on deep learning algorithms. Our approach exploits spatial relationships among positions of dies, sizes of dies, and die-level yield variations collected from a wafer test. By modeling these spatial features, the accuracy of yield prediction significantly increased. Furthermore, experimental results showed that the proposed yield model and approach help to design a wafer map with higher productivity nearly 13\%.",

keywords = "Deep learning, Semiconductor manufacturing, Wafer map, Wafer productivity, Yield modeling",

author = "Jang, \{Sung Ju\} and Lee, \{Jee Hyong\} and Kim, \{Tae Woo\} and Kim, \{Jong Seong\} and Lee, \{Hyun Jin\} and Lee, \{Jong Bae\}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018 ; Conference date: 30-04-2018 Through 03-05-2018",

year = "2018",

month = jun,

day = "5",

doi = "10.1109/ASMC.2018.8373137",

language = "English",

series = "2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "29--34",

booktitle = "2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018",

}

Jang, SJ, Lee, JH, Kim, TW, Kim, JS, Lee, HJ & Lee, JB 2018, A wafer map yield model based on deep learning for wafer productivity enhancement. in 2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018. 2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018, Institute of Electrical and Electronics Engineers Inc., pp. 29-34, 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018, Saratoga Springs, United States, 30/04/18. https://doi.org/10.1109/ASMC.2018.8373137

A wafer map yield model based on deep learning for wafer productivity enhancement. / Jang, Sung Ju; Lee, Jee Hyong; Kim, Tae Woo et al.
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 29-34 (2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A wafer map yield model based on deep learning for wafer productivity enhancement

AU - Jang, Sung Ju

AU - Lee, Jee Hyong

AU - Kim, Tae Woo

AU - Kim, Jong Seong

AU - Lee, Hyun Jin

AU - Lee, Jong Bae

PY - 2018/6/5

Y1 - 2018/6/5

N2 - In semiconductor manufacturing, evaluating the productivity of wafer maps prior to fabrication for designing an optimal wafer map is one of the most effective solutions for enhancing productivity. However, a yield prediction model is required to accurately evaluate the productivity of wafer maps since the design of a wafer map affects yield. In this paper, we propose a novel yield prediction model based on deep learning algorithms. Our approach exploits spatial relationships among positions of dies, sizes of dies, and die-level yield variations collected from a wafer test. By modeling these spatial features, the accuracy of yield prediction significantly increased. Furthermore, experimental results showed that the proposed yield model and approach help to design a wafer map with higher productivity nearly 13%.

AB - In semiconductor manufacturing, evaluating the productivity of wafer maps prior to fabrication for designing an optimal wafer map is one of the most effective solutions for enhancing productivity. However, a yield prediction model is required to accurately evaluate the productivity of wafer maps since the design of a wafer map affects yield. In this paper, we propose a novel yield prediction model based on deep learning algorithms. Our approach exploits spatial relationships among positions of dies, sizes of dies, and die-level yield variations collected from a wafer test. By modeling these spatial features, the accuracy of yield prediction significantly increased. Furthermore, experimental results showed that the proposed yield model and approach help to design a wafer map with higher productivity nearly 13%.

KW - Deep learning

KW - Semiconductor manufacturing

KW - Wafer map

KW - Wafer productivity

KW - Yield modeling

UR - https://www.scopus.com/pages/publications/85048897471

U2 - 10.1109/ASMC.2018.8373137

DO - 10.1109/ASMC.2018.8373137

M3 - Conference contribution

AN - SCOPUS:85048897471

T3 - 2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018

SP - 29

EP - 34

BT - 2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018

Y2 - 30 April 2018 through 3 May 2018

ER -

Jang SJ, Lee JH, Kim TW, Kim JS, Lee HJ, Lee JB. A wafer map yield model based on deep learning for wafer productivity enhancement. In 2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 29-34. (2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2018). doi: 10.1109/ASMC.2018.8373137

A wafer map yield model based on deep learning for wafer productivity enhancement

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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