A tracked oversampling digital data recovery for Low Latency, fast acquisition, and high jitter tolerance

A new technique to achieve high jitter tolerance and fast frequency acquisition with low logic latency for MIPI Low Latency Interface (MIPI LLI) applications is proposed. The proposed tracked oversampling CDR increases the allowable phase difference between the recovered and embedded reference clock up to 1.25 UI. The CDR loop gain can be adjusted based on the digitally estimated phase difference, resulting in short acquisition time (≤ 1 baud period) and high jitter tolerance (167-UI_p-p 100-kHz jitter). Utilizing a bit selector with an edge tracking finite state machine (FSM) instead of an elastic FIFO, a logic latency less than 2 baud periods is achieved. The core circuit is implemented using a 65nm CMOS technology. It consumes 4.7mW from a 1.2V power supply at 5.8Gb/s.